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Course Modules

Module 1: Universal Asynchronous Receiver-Transmitter (UART)

Specifications

Serial communication protocol.
Full-duplex, asynchronous data transfer.
Data frame: Start bit, data bits (5–8), optional parity bit, stop bit.
Configurable baud rate.

Features

Simple, low-cost serial interface.
Widely used for device-to-device communication.
Flow control using RTS/CTS signals.

RTL Design

Design UART transmitter and receiver in Verilog.
Include baud rate generator and FIFO buffers.
Implement flow control mechanisms.

Verification

UVM Testbench: Sequence generation for data transmission and reception. Monitor protocol compliance.
Assertions: Check timing, parity error, and framing error.
Functional Coverage: Frame structure, overflow/underflow edge cases.

Module 2: Inter-Integrated Circuit (I2C)

Specifications

Two-wire communication: SDA and SCL.
Supports multiple masters and slaves.
Modes: Standard (100 kbps), Fast (400 kbps), High-Speed (3.4 Mbps).

Features

Synchronous serial communication.
7-bit/10-bit device addressing.
Acknowledgment after every byte.

RTL Design

Design I2C Master and Slave in Verilog.
Implement start/stop conditions, addressing, and clock stretching.

Verification

UVM Testbench: Read/write sequences, model slaves.
Assertions: Start/stop detection, acknowledgment check.
Functional Coverage: Address validity, data path scenarios.

Module 3: Advanced Peripheral Bus (APB)

Specifications

Low-power, low-latency bus.
Single-master, single-slave communication.
Minimal control logic.

Features

Non-pipelined, single clock-edge operation.
Simple read/write transfers.

RTL Design

Design APB Master and Slave in Verilog.
Address decoding, PREADY, and error (PSLVERR).

Verification

UVM Testbench: Read/write sequences and error testing.
Assertions: PSEL, PENABLE, PWRITE signal checks.
Functional Coverage: Transfer types and errors.

Module 4: Advanced High-performance Bus (AHB)

Specifications

High-performance, pipelined bus.
Single-master, multi-slave architecture.
Burst, split, and retry support.

Features

High throughput with synchronous operation.
Arbitration logic for communication.

RTL Design

Design AHB Master and Slave in Verilog.
Implement arbitration, burst handling, split/retry logic.

Verification

UVM Testbench: Burst sequences and arbitration testing.
Assertions: Burst size, response code checks.
Functional Coverage: Arbitration and transaction scenarios.

Module 5: Advanced eXtensible Interface (AXI)

Specifications

Multiple masters/slaves with high-performance bus.
Channels: Write Addr, Write Data, Write Resp, Read Addr, Read Data.
Out-of-order transaction support.

Features

High bandwidth, low latency.
QoS and error signaling.
Separate address/control and data phases.

RTL Design

Design AXI Master, Slave, Interconnect in Verilog.
Implement burst, QoS, and outstanding transactions.

Verification

UVM Testbench: Multi-channel sequence generation and interconnect validation.
Assertions: Handshake and timing checks.
Functional Coverage: Channels, bursts, and execution order.

Project & Protocols

Deliverables

What You Will Get

Lab Exercises

Hands-on coding for pipeline stages and hazard logic
Verification of pipeline features

Study Material

Detailed lecture notes
Code templates and reference documents

Projects

Complete processor design
Verification with final evaluation

Certification

Completion certificate
Includes project grades

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