ASIC Design Course | Learn Chip Design & Verification

Course Modules

Module 1 - Advanced Digital Logic Design

Number Systems

Logic Gates, Boolean Algebra, K-maps

Gate Conversions using Universal Gates

All Types of Combinational Circuits

All Types of Sequential Circuits

Shift Registers & Counters

FSMs and Application Examples

Memories

Static Timing Analysis

CMOS Logic Design

Glitches & Hazards

Regular Assignments & Mock Tests

Interview Preparation

Module 2 - RTL Design using Verilog HDL

Language Introduction & Applications

Data Types, Operators

All Description Styles – Theory Explanation

Behavioral, Dataflow, Gate & Switch Level Modeling (Lab Sessions)

Rules to Follow in Verilog HDL

Procedural & Continuous Statements

Blocking & Non-Blocking Assignments - Lab

Generate Blocks, Bad Latches, UDPs

Process of Synthesis & RTL Coding

Testbench Creation & Constructs

Simulator Directives, System Tasks, Randomization

Modelling of Combinational Circuits, Latches, Flip-flops, Registers, Counters

Regular Assignments & Mock Tests

Interview Preparation

Module 3 - Verification using SystemVerilog

SystemVerilog Overview

Standard & User-Defined Data Types

Testbench Architecture & Connectivity

BFM Model & TB Components

Arrays: Static, Dynamic, Associative

Queues, Mailbox, Semaphores

Tasks & Functions

Interfaces & Virtual Interfaces

Clocking Blocks, Modports

OOPs Concepts (Class, Object, Polymorphism, Inheritance)

Random Stimulus & Constraint-based Verification

Functional, Code, Toggle & Cross Coverage

Assertion Based Verification (SVA)

Direct Programming Interface (DPI)

Interprocess Synchronization

Testplans & Testcases Development

All topics: Theory + Lab

Regular Assignments, Mock Tests

Interview Preparation

Module 4 - Verification using UVM

Deep Understanding of UVM in SOC | IP

UVC in SOC | IP

UVM Introduction & Features

Testbench Hierarchy & Components

Sequence Item, Sequence & Sequencer

Configuration & UVM config_db

UVM Phases

Driver, Monitor, Agent

Scoreboard & Environment

RAL Model & TLM

Callbacks, Events

UVM Testbench Examples

Testplan & Detailed Test Plans (DTPs)

Regression & Debugging

All topics: Theory + Lab

Regular Assignments, Mock Tests

Interview Preparation

Module 5 - Perl Scripting

Introduction to Linux Setup

Importance of Perl Scripting

How to run the commands

Idea on Coverage analysis

Upload and extract the coverage report

Walk through perl concepts

Coding standards

Explanation of Data types, Arrays

Hashes, Loops

Operators, Subroutines

Date & Time

References, Formats

Directories

Error Handling

Module 6 - 5 Industrial Protocols, 3 Major Projects

Protocols & Projects

Protocol 1 - UART (RTL Design)

Theory

Introduction to UART Protocol – Features and Applications
Functional Block Diagram of UART
Signal Definitions and Timing Diagram

Implementation

Transmitter FSM & Baud Rate Generator
Receiver FSM & Data Sampling
RTL Coding of UART TX/RX
Testbench Creation & Simulation
Debugging and Waveform Analysis

Protocol 2 - I2C (RTL Design & SV Verification)

Theory

I2C Overview: Features, Signals, Modes of Operation
Address Recognition & Clock Stretching
Arbitration Handling for Multi-Master Systems
Multi-Master & Multi-Slave Configurations
Timing Diagram & Bit-Level Analysis

Implementation

RTL Design of I2C Controller
SystemVerilog Testbench Development
Test Cases for Functional Verification
Coverage Metrics & Analysis

Protocol 3 - AMBA APB (RTL Design & SV Verification)

Theory

Introduction to APB Protocol
Purpose of APB in Low-power Peripherals
Signal & Bus Architecture
Timing Diagrams & Key Operations
Features: Simple Interface, Limited Pipelining

Implementation

RTL Design for APB Master & Slave
RTL Code Development
Simulation & Debugging
SystemVerilog Testbench: Sequences & Assertions
Functional Verification & Coverage

Protocol 4 - AMBA AHB (RTL Design & UVM Verification)

Theory

High-performance, Pipelined Bus System
Burst Transfers & Arbitration Mechanisms
Signal Descriptions & Timing Diagrams
Features: Multi-Master, Single-edge Clock

Implementation

AHB Master & Slave Design
State Machine for Pipelined Operations
Address Decoding & Data Transfer Logic
RTL Implementation of Interfaces
UVM Environment for AHB Verification
Coverage: Split, Retry, Burst Scenarios

Protocol 5 - AMBA AXI (VIP Development)

Theory

AXI Channels: Write, Read, Address, Response
Features: Outstanding Transactions, Bursts
Out-of-order Execution, Low Latency, High Bandwidth
Advanced Features: QoS, Atomic Transactions

Implementation

RTL Design & VIP Development
UVM Testbench for Multi-channel Handling
Assertions for AXI Handshakes
Coverage for Burst Types, QoS, Errors
Complementary Project: AHB → APB Bridge

Project 1 - RISC V Processor

Theory

Instruction Set Architecture & Addressing Modes
Pipeline Stages (IF, ID, EX, MEM, WB)
RISC-V Hardware Architecture

Implementation

RTL Coding for Each Pipeline Stage
Pipeline Integration & Hazard Handling
Forwarding & Stalling Techniques
SystemVerilog Testbenches & Assertions
Functional Coverage of Instructions

Project 2 - DMA Controller

Theory

Data Transfer between Memory & Peripherals
Burst & Multi-channel Operations
Priority Handling
DMA Controller Architecture

Implementation

RTL Design: Request Handling, Counters, Signaling
Verilog/SystemVerilog RTL Coding
Test Plan: Functional & Corner Cases
Directed + Random Test Scenarios
Scoreboarding & Functional Coverage

Project 3 - 1x3 Router

Theory

Router Functionality: Single Input, Three Outputs
Packet Structure & Core Architecture
Synchronizer, FSM, FIFO, Register Designs

Implementation

RTL Design using Verilog HDL
UVM Testbench: Sequence, Driver, Monitor, Scoreboard
Scenarios: Single/Multiple Packet Routing
FIFO Overflow/Underflow Conditions
Error Injection (Wrong Header/Parity)
Stress Tests with Random Streams
Coverage: Routing, Header Detection, Packet Size, Parity

ASIC Design & Verification Course

Course Features

Structured Course Curriculum

24/7 Industry Tool Access

Mock Interview Preparation

Best Live Sessions

Industrial Project Assistance

1:1 Mentorship

Resume Preparation

Placement Guaranteed

Course Modules

Module 1 - Advanced Digital Logic Design

Module 2 - RTL Design using Verilog HDL

Module 3 - Verification using SystemVerilog

Module 4 - Verification using UVM

Module 5 - Perl Scripting

Module 6 - 5 Industrial Protocols, 3 Major Projects

Protocols & Projects

Protocol 1 - UART (RTL Design)

Theory

Implementation

Protocol 2 - I2C (RTL Design & SV Verification)

Theory

Implementation

Protocol 3 - AMBA APB (RTL Design & SV Verification)

Theory

Implementation

Protocol 4 - AMBA AHB (RTL Design & UVM Verification)

Theory

Implementation

Protocol 5 - AMBA AXI (VIP Development)

Theory

Implementation

Project 1 - RISC V Processor

Theory

Implementation

Project 2 - DMA Controller

Theory

Implementation

Project 3 - 1x3 Router

Theory

Implementation

System on Chip Design

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