ASIC Design Course - Master Chip Design & Verification

Course Modules

Introduction to VLSI Design

Overview of VLSI Design Flow

History & Future of Semiconductors

Frontend Domain vs Backend Domain

Discussion on Industry Requirements

Moore Law, Nano meter technology

CMOS vs FINFET vs GAAFET VLSI Fabrication Technologies

FPGA vs ASIC vs SOC designs

SOC vs Subsystem vs IP level Verification

Application of Digital electronics

Introduction to RTL Design & Verification

Module 1 - Advanced Digital Logic Design

Digital Logic Design - All Basic Topics

Number Systems, Conversions

Logic Gates, Boolean Algebra, K-maps

All types of Combinational Logic Circuits

• Parallel Adder, Subtractor, Multiplexer, Demux

•Encoder, Decoder, BCD to Seven Segment Display - Applications

All types of Sequential Logic Circuits, Latches, Flip-Flops

•Shift Registers, Counters Designs - Applications

•FSMs and Its Application Examples

Memories: RAM vs ROM vs FIFO vs LIFO

Static Timing Analysis - Problems Practice

CMOS Logic Design - Problems Practice

Glitches & Hazards, Delays

Weekly Group Discussion & Mock Interviews

Module 2 - RTL Design using Verilog HDL

Verilog HDL - Complete Topics

Why HDL ?

Verilog HDL vs VHDL vs System Verilog

Language Introduction and Applications

Data Types, Operators

Introducing the Process of Synthesis

Coding RTL for Synthesis

All Description Styles – Theory Explanation

Rules must be followed to write a Verilog code

Types of Procedural Statements

•always, initial - Rules

Types of Continuous Statements

•assign - Rules

Behavioral Modelling - Lab Sessions

Dataflow Modelling - Lab Sessions

Gate Level Modelling - Lab Sessions

Switch Level Modelling - Lab Sessions

Blocking and Non-Blocking Assignments - Lab Sessions

Fork-join, begin-end, UDP’s

Generate, Genvar blocks, Bad latches in Verilog

If-else, for, forever, repeat, while, do-while loops

Modelling of Testbenches

Different styles of building Testbenches

Modelling of Combinational Circuits, Latches, Flip-Flops, Registers, Counters

Logical Questions & Problem Solving

RTL Design: FSMs & Memories

RTL Design and Verification of FIFO | RAM | ROM

Testbench Concepts for Verification (Basics to PRO)

Regular Assignments & Mock Tests

Interview Preparation

Module 3 - SystemVerilog for Verification

SystemVerilog - Complete Topics

Limitations of Verilog HDL

Importance of Functional Verification in SOC | IP level Design

SystemVerilog History & Overview

Testbench Architecture & Connectivity

Testbench Components & Its Importance

Standard Data Types

•User Defined Data Types - typedef, enum, struct, union

•bit, byte, int, integer, longint, shortint, logic, reg

Operators, fork-join, fork-join_any, join_all, join_none

Arrays

• Static, Dynamic, Associative

Queues, Tasks & Functions, Events

Interfaces

•Virtual Interface Verification Features

•Clocking Blocks, Modports

Semaphores, Mailbox, Casting

Deep into Object Oriented Programming

•Class, Objects, Members, Instances, this keyword

•Inheritance, Encapsulation

•Polymorphism, Abstract Class, Virtual Task

•Virtual Function, Pure Virtual

•Overriding Concepts, Constant, Static

•Scope Resolution Operators, Parameterized Class

•Applications of OOP Concepts - Logical Problems

Class-Based Random Stimulus

•Randomization: rand, randc

•Pre, Post Randomization

•Enable & Disable - Randomization & Constraints

Constraint Based Random Verification

•Soft Constraint, Inline Constraints

•Bi-directional, Global, Interactive, Unique Constraints

•Hands-on Logical Questions for Practice

SystemVerilog Coverage Analysis

•Deep into Functional Coverage

•Code Coverage

•Toggle Coverage

•Cross Coverage

•Different Types of Bins

•Holes & How to Reach 100% Coverage

•Generating Coverage Reports

•Real-time Challenges & Debugging Issues

•How to Achieve 100% Functional Coverage

Assertion Based Verification (ABV)

•Immediate Assertions

•Concurrent Assertions

•Simulator Directives

•Hands-on Practice with Interview Problems

Direct Programming Interface (DPI)

Interprocess Synchronization

Testbench Development from Scratch

Testbench Examples to Advanced with Coverage Analysis

Creating Test Plans, Test Cases, Test Scenarios

Hands-on Lab Sessions for All Concepts

Regular Assignments

Mock Tests, Group Discussions

Interview Preparation

Module 4 - UVM for Verification

UVM - Complete Topics

Limitations of SystemVerilog

Why UVM and Its Features

Importance of UVM in SOC | IP level Verification

Detailed explanation on UVC in SOC | IP Verification

Introduction to UVM, Features

Testbench Hierarchy, Components

•UVM Sequence Item, Sequence, Sequencer

•UVM Phases

•UVM Driver

•UVM Monitor, Scoreboard

•UVM Agent (Active, Passive)

•UVM Environment

•UVM Test

Factory Mechanism & Limitations from SystemVerilog

•Factory Registration, Field Macros

•Factory Overriding (Instance override, Type override)

Configuration Mechanism, UVM config_db

TLM Interfaces

•Target vs Initiator, Blocking vs Non-blocking

•Analysis Port, Connecting with Components

UVM Phases & Simulation Flow

•Limitations from SystemVerilog Events

•Build, Connect, Run, Extract, Check, Final, Report Phases

•Objections and Phase Control

Callbacks

• Component & Sequence Callbacks

UVM Reporting & Messaging

• Reporting Macros, Verbosity Levels, Report Catchers

Virtual Sequence & Virtual Sequencer

UVM RAL (Register Abstraction Layer)

• Register Modeling, Adapter, Predictor

• Front Door & Back Door Access

• Register Data ↔ Binary Data (Conversion using methods)

UVM Testbench Development from Scratch

UVM Testbench Examples (Basic to Advanced)

Test Plan, Test Cases & Test Scenarios Development

Interview Preparation

Mock Discussion & 1:1 Doubt Discussions

Module 5 - Scripting Language - Perl

Perl - Complete Topics

Perl Fundamentals

• Introduction to Perl: History, features, and applications in VLSI

• Basic syntax, data types (scalars, arrays, hashes), and variables

• Operators (arithmetic, comparison, logical, bitwise)

• Control structures: Conditional statements (if, unless, switch), loops (for, foreach, while, until)

• Subroutines and functions

Regular Expressions

•Pattern matching and substitution

•Modifiers, character classes, quantifiers, and anchors

•Grouping and backreferences

File Operations

• Reading from and writing to text files

•File test operators and handling file properties

•Directory manipulation (creating, deleting, listing)

•CSV file handling for data parsing and generation

VLSI Specific Applications

•Parsing log files and reports from VLSI tools (synthesis, simulation, place & route)

•Automating regression flows and testbench generation

•Generating configuration files and input data for VLSI tools

•Creating UVM register models from spreadsheets

•Processing and generating design data

Modules and packages for code organization and reusability

Object-Oriented Programming (OOP) in Perl

Interfacing with databases (storing and retrieving design data)

Generating HTML reports for regression results

Module 6 - 5 Industrial Protocols, 3 Major Projects

Protocols & Projects

Protocol 1- UART Protocol - RTL Design Using Verilog HDL

Theory - Spec explanation

Introduction to UART Protocol – Features and Applications
Functional Block Diagram of UART
Signal Definitions and Timing Diagram

Implementation

Transmitter Design: FSM Implementation, Baud Rate Generator
Receiver Design: FSM Implementation, Data Sampling
RTL Coding of UART Transmitter and Receiver
Testbench Creation and Simulation/li>
Debugging and Waveform Analysis

Protocol 2 - I2C Protocol Implementation and Verification

Theory - Spec Explanation

I2C Protocol Overview: Features, Signals, and Modes of Operation
Multi-Master and Multi-Slave Configurations
Timing Diagram and Bit-Level Analysis
Arbitration, Clock stretching, Multi master, Multi slave

Implementation

RTL Design of I2C Controller
Writing Test Cases in SystemVerilog
Testbench Creation and Verification using SystemVerilog
Coverage Metrics and Analysis
Analyzing clock stretching operation

Protocol 3 - AMBA Protocols (AMBA APB AHB AXI) AMBA APB Protocol

Theory - Spec Explanation

APB Protocol Overview: Features, Signals, and Modes of Operation
FSM states, Bus Architecture
Timing Diagram and Write, Read transfers
Protect, slave error signal conditions, wait states
Idle, Setup, Access phases & Waveform analysis

Implementation

RTL Design & Functional Verification APB Protocol
Writing Test Cases in SystemVerilog
Simulation & Debugging
Testbench Creation and Verification using SystemVerilog
Coverage analysis, Signal debugging, read/write operations.
Timing checks for PREADY and PSLVERR.

Protocol 4 -AMBA Protocols (AMBA APB AHB AXI) AMBA AHB Protocol

Theory - Spec Explanation

AHB Protocol Overview: Features, Signals, and Modes of Operation
Master & Slave Architecture, AHB Transfers
Burst operation, Warp, Increment, HMASTLOCK
Protect, slave error signal conditions, wait states
Okay, Error response, Pipeline vs Non-pipeline

Implementation

RTL Design & UVM Testbench Components
UVM environment for AHB verification.
Sequence generation for split and burst transfers.
Assertions for AHB Timing assertions for arbitration and responses.
Data consistency and burst transaction checks.
Coverage Analysis Functional coverage for split, retry, and burst scenarios.

Protocol 5 - AMBA Protocols (AMBA APB AHB AXI) AMBA AXI Protocol

Theory - Spec Explanation

AXI Protocol Overview: Features, Channels, and Pipeline concept
Write address(WA), Write data(WD), Write response(B)
Read address (AR), Read data (R) channels
AXI Interconnect, Burst transfers, Outstanding Transactions
Signal transfers, error response

Implementation

RTL Design & Functional Verification using UVM
Test plan - Fixed Burst Incremented
Burst Wrap, Unaligned Transfers, Outstanding Transactions
Out-of-Order, Execution Atomic, Transactions Response Handling
VIP Development of AXI Protocol
VIP Development of AXI Protocol
Development of all UVM components with scoreboard

Project 1 - 4 - Port Calculator RTL Design & Verification

Theory - Spec Explanation

Project Overview: Outstanding commands explanation
Pin diagram & Functionality
Design of 4- Ports, Functional block diagram, Operations
Out of order transaction, Overflow bit
Signal description, Timing diagrams, possible conditions

Implementation

RTL Design using Verilog HDL
Writing testbench using Verilog tasks & functions
Verifying timing diagrams
Developing into SV testbench with Constraints
Constraint based Verification for Commands
Analyzing dumps and debugging testflow

Project 2 - RISC V Processor RTL Design & Functional Verification

Introduction to RISC-V

History and significance of RISC V
Open-source ISA odvantages

RISC-V ISA Basics

Instruction formats (R, I, S, B, U, J types)
Registers and addressing modes

Core Concepts

ALU operations
Control unit design
Memory interface (load/store operations)

Pipeline Stages

IF, ID, EX, MEM, WB overview

Hands-on

Writing simple assembly programs
Implementing a single-cycle R15C-V processor in
Verilog

Pipeline Design

5 - stage pipeline implementation (IF, ID, EX. MEM WBI
Handling hazards: structural, data, control
Forwarding and stalling techniques

RTL Implementation

Verliog coding for each stage
Integration into full pipeline

Verification with SystemVerilog

Writing testbenches
Scoreboarding and assertions
Functional coverage of Instructions

Project

Design & verity a pipelined RISC-V CPU
Debugging common pipeline issues

Project 3 - 1*3 Router Project in UVM Verification

Theory

Router Functionality: Single Input, Three Outputs
Specification & Functional block diagram
Packet Structure, Payload data, Detailed explanation
Synchronizer, FSM, FIFO, Input Register Design

Implementation

RTL Design using Verilog HDL
UVM Testbench: Sequence, Sequencer, Driver, Monitor, Scoreboard
Test cases, Test plan, Test scenarios
Scenarios: Single/Multiple Packet Routing
FIFO Overflow/Underflow Conditions
Error Injection (Wrong Header/Parity)
Stress Tests with Random Streams
Coverage: Routing, Header Detection, Packet Size, Parity

ASIC Design & Verification Course

Course Features

Structured Course Curriculum

24/7 Industry Tool Access

Mock Interview Preparation

Best Live Sessions

Industrial Project Assistance

1:1 Mentorship

Resume Preparation

Placement Guaranteed

Course Modules

Introduction to VLSI Design

Module 1 - Advanced Digital Logic Design

Digital Logic Design - All Basic Topics

Module 2 - RTL Design using Verilog HDL

Verilog HDL - Complete Topics

Module 3 - SystemVerilog for Verification

SystemVerilog - Complete Topics

Module 4 - UVM for Verification

UVM - Complete Topics

Module 5 - Scripting Language - Perl

Perl - Complete Topics

Module 6 - 5 Industrial Protocols, 3 Major Projects

Protocols & Projects

Protocol 1- UART Protocol - RTL Design Using Verilog HDL

Theory - Spec explanation

Implementation

Protocol 2 - I2C Protocol Implementation and Verification

Theory - Spec Explanation

Implementation

Protocol 3 - AMBA Protocols (AMBA APB AHB AXI) AMBA APB Protocol

Theory - Spec Explanation

Implementation

Protocol 4 -AMBA Protocols (AMBA APB AHB AXI) AMBA AHB Protocol

Theory - Spec Explanation

Implementation

Protocol 5 - AMBA Protocols (AMBA APB AHB AXI) AMBA AXI Protocol

Theory - Spec Explanation

Implementation

Project 1 - 4 - Port Calculator RTL Design & Verification

Theory - Spec Explanation

Implementation

Project 2 - RISC V Processor RTL Design & Functional Verification

Introduction to RISC-V

RISC-V ISA Basics

Core Concepts

Pipeline Stages

Hands-on

Pipeline Design

RTL Implementation

Verification with SystemVerilog

Project

Project 3 - 1*3 Router Project in UVM Verification

Theory

Implementation

System on Chip Design

Courses

Company

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