ADVANCED PHYSICAL DESIGN Professional

Job oriented Training + Industrial Guidance + Placement Assistance

Gain hands-on expertise in ADVANCED PHYSICAL DESIGN Course Curriculum , mastering industry tools and methodologies for a successful career

Course Module

Module 1 - Advanced Digital Logic Design

Digital Logic Design - All Basic topics

Logic gates, Boolean Algebra, K-maps

All type of Combinational logic circuits

All type of Sequential logic circuits

Shift Registers, Counters designs

FSMs and Its Application examples

Memories

Static Timing Analysis

CMOS Logic Design

Glitches & Hazards

Interview Preparation

Regular Assignments

Mock tests

Interview Preparation

Module 2 - RTL Design using Verilog HDL

Language Basics and Applications

Data Types, Operators, and Syntax

All Description Styles – Theory explanation

Behavioral Modeling

Dataflow Modelling - Lab sessions

Gate Level Modelling - Lab sessions

Switch Level Modelling - Lab sessions

Types of Procedural Statements

Types of Continuous Statements

Blocking and Non-Blocking Assignments - Lab Sessions

Introducing the Process of Synthesis

Coding RTL for Synthesis

Modelling of Combinational Circuits, Latches, Flipflop, Registers, Counters

Registers, Counters

Regular Assignments, Mock Tests

Interview Preparation

Module 3 - Physical Design Flow

Overview of Advanced Physical Design

Floor planning and Power Planning

Placement

Clock Tree Synthesis (CTS)

Routing

Timing and Signal Integrity

Power and Thermal Analysis

Design for Manufacturability (DFM)

Physical Verification

Module 4 - TCL Scripting

Fundamentals of TCL Scripting

Variables, Loops, and Conditionals

Procedures and Functions

TCL in EDA Tools

Automating Placement and Routing Tasks

Debugging and Design Rule Checks

Real-World Applications of TCL

Optimization Scripts for Design Closure

Lab: Writing and Deploying TCL Scripts in Physical Design

Module 5 - Linux Setup

Introduction to Linux

Essential Linux Commands

Text Editors

Shell Scripting

Environment Setup

Version Control with Git

VLSI Physical Design Flow & at Advanced Technology Nodes

Overview of Advanced Physical Design

Theory

VLSI Backend Design Flow
Advanced Technology Nodes (7nm, 5nm, 3nm, etc.)
Challenges in Modern Physical Design

Implementation

Foundry and Process Design Kits (PDK)
Case Study: Advanced Nodes in Real-World Designs

Floorplanning and Power Planning

Theory

Advanced Floorplanning Strategies
Macro Placement Optimization
Pin and IO Placement
Hierarchical vs. Flat Floorplanning

Implementation

Advanced Power Grid Design
Dynamic Power Analysis
Low-Power Techniques (Dynamic Voltage Scaling, Multi-Vt)
Case Study: Power Planning for High-Performance Chips

Placement Optimization in Physical Design

Theory

Timing-Driven Placement
Congestion Estimation and Mitigation
Machine Learning Techniques in Placement Optimization
Multi-Die Placement in 3D ICs

Implementation

Density Optimization and Design Closure
Lab: Placement Optimization Using Industry Tools

Clock Tree Synthesis (CTS)

Theory

Advanced Clock Tree Design
Low-Skew and Low-Latency Clock Trees
Mesh vs. H-Tree vs. Clock Gating
Clock Domain Crossing (CDC) Challenges
Multi-Corner Multi-Mode (MCMM) CTS Techniques
Power-Aware CTS

Implementation

Lab: Advanced CTS Implementation in EDA Tools

Advanced Routing Techniques

Theory

Advanced Routing Algorithms
Maze Routing
Congestion Management in Global Routing
Detailed Routing at Advanced Nodes
Track Assignment and Routing Layer Utilization
Double Patterning and Lithography-Aware Routing
Crosstalk and Noise Mitigation Techniques

Implementation

Lab: DRC-Compliant Routing at Advanced Nodes

Timing and Signal Integrity Analysis

Theory

Advanced Static Timing Analysis (STA)
Multi-Mode Multi-Corner Analysis
Path-Based Analysis (PBA)
Clock Skew, Jitter, and Timing Closure
Signal Integrity Challenges and Mitigation

Implementation

Lab: Timing Optimization and SI Analysis

Power and Thermal Analysis

Theory

Advanced IR Drop Analysis
Power Grid Optimization at Advanced Nodes
Thermal Analysis and Hotspot Mitigation
Electrostatic Discharge (ESD) Protection

Implementation

Lab: Power and Thermal Analysis with Signoff Tools

Design for Manufacturability (DFM)

Theory

Lithography Challenges at Advanced Nodes
Antenna Effect Analysis and Fixes
Design Rule Check (DRC) Optimization
Layout Optimization for Yield Enhancement

Implementation

Lab: DFM-Aware Physical Design

Physical Verification

Theory

Advanced LVS and DRC Techniques
Parasitic Extraction and Post-Layout Simulation
Physical Verification for FinFET and 3D ICs
Signoff Tools and Methodologies

Implementation

Lab: Physical Verification of an Advanced Node Design

Projects & Protocols

Project 1 - UART Protocol - RTL Design Using Verilog HDL

Theory

Introduction to UART Protocol: Features and Applications
Functional Block Diagram of UART
Signal Definitions and Timing Diagram

Implementation

Transmitter Design: FSM Implementation, Baud Rate Generator
Receiver Design: FSM Implementation, Data Sampling
RTL Coding of UART Transmitter and Receiver using Verilog HDL
Testbench Creation and Simulation
Debugging and Waveform Analysis

Project 10 - Advanced SoC Design and Implementation

Theory

High-Performance Processor Floorplan and Power Grid Design
Low-Power Multi-Core SoC Design
SRAM Design and Physical Implementation

Implementation

RTL-to-GDSII Implementation
Advanced Routing Optimization for 3nm Design
Advanced Power Integrity Analysis

Note: Can select any 2 projects based on area of interest.

Why ProV Logic ?

Structured
Course Curriculum

Tool Access
Lab Sessions

Mock Interviews
Resume guide

Best Live Sessions
Doubt discussions

1:1 Mentorship

Placement
Guaranteed

ADVANCED PHYSICAL DESIGN Professional

Course Module

Module 1 - Advanced Digital Logic Design

Module 2 - RTL Design using Verilog HDL

Module 3 - Physical Design Flow

Module 4 - TCL Scripting

Module 5 - Linux Setup

VLSI Physical Design Flow & at Advanced Technology Nodes

Overview of Advanced Physical Design

Theory

Implementation

Floorplanning and Power Planning

Theory

Implementation

Placement Optimization in Physical Design

Theory

Implementation

Clock Tree Synthesis (CTS)

Theory

Implementation

Advanced Routing Techniques

Theory

Implementation

Timing and Signal Integrity Analysis

Theory

Implementation

Power and Thermal Analysis

Theory

Implementation

Design for Manufacturability (DFM)

Theory

Implementation

Physical Verification

Theory

Implementation

Projects & Protocols

Project 1 - UART Protocol - RTL Design Using Verilog HDL

Theory

Implementation

Project 10 - Advanced SoC Design and Implementation

Theory

Implementation

Why ProV Logic ?

Courses

Company

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