RTL to GDS

Explore the entire RTL to GDS flow and understand the backend process in VLSI design. Gain Industry standard tool experience

Course Features

Module 1: Overview of RTL to GDS Flow

1. Introduction to RTL to GDS Flow

Key stages in the process: RTL design, synthesis, place & route, physical verification
Overview of the complete design flow

2. Fabrication Flow

Semiconductor fabrication process
From GDSII to tapeout: Mask generation and silicon processing

3. Linux Environment Setup

Setting up the Linux environment for VLSI tools
Basic Linux commands: File handling, navigation, and scripting

Module 2: Basics of Scripting and Tools

1. TCL Scripting (Session 4-5)

Introduction to TCL scripting for automation
Essential TCL commands used in VLSI design

2. Tool Demonstration (Session 6)

Overview of open-source tools used in RTL to GDS flow
Installation and configuration of tools

Module 3: High-Level Synthesis and Verilog Design

1. Bambu for High-Level Synthesis (Sessions 7-8)

Introduction to HLS using Bambu
Practical demonstration for converting C/C++ code to RTL

2. Verilog Basics (Session 9)

Fundamentals of Verilog for RTL design
Syntax, structure, and coding guidelines

Module 4: Simulation and Logic Synthesis

1. Quartus Prime and Modelsim (Sessions 10-11)

Writing and validating Verilog code
Using Modelsim for simulation: writing, compiling, and running testbenches

2. Yosys for Logic Synthesis (Sessions 12-14)

Detailed sessions on logic synthesis using Yosys
Technology mapping and optimization techniques

Module 5: Floorplanning and Placement

1. OpenROAD for Floorplanning and Routing (Sessions 15-18)

Introduction to OpenROAD for floorplanning and placement
Routing and Clock Tree Synthesis (CTS) processes

Module 6: Physical Design and Timing Analysis

1. Magic for Layout Design (Sessions 17-18)

Introduction to layout generation using Magic
Running DRC and LVS for physical verification

2. OpenSTA for Static Timing Analysis (Sessions 19-20)

Fundamentals of static timing analysis (STA)
Using OpenSTA for timing verification

Module 7: Layout Editing and Verification

1. KLayout for GDSII Editing (Sessions 21-22)

Introduction to KLayout for layout file manipulation
Hands-on editing and verification of GDSII files

2. Project Assignment (Sessions 23-24)

Practical project involving the full RTL to GDS flow
Detailed project guidelines and evaluation criteria

Module 8: Final Project and Protocol Design

1. RTL Design of UART Protocol (Sessions 25-26)

Hands-on experience in designing the UART protocol
Detailed explanation and implementation

2. Full Project Assignment (Session 27)

Comprehensive project on RTL Design & Verification
In-depth explanation and execution of the project

Projects & Protocols

Deliverables

What You Will Get

Tools and Techniques

Use of tools like Quartus Prime, Modelsim, Yosys
OpenROAD, Magic, OpenSTA, KLayout
Hands-on with Bambu for High-Level Synthesis

Study Material

Comprehensive slides and tutorials
Code templates for RTL and synthesis

Projects

Complete processor design
Verification with final evaluation

Certification

Completion certificate
Includes project evaluation

Stay updated with the latest courses, exclusive content, and learning resources delivered straight to your inbox. Subscribe now and never miss an update!

Courses

Company

Social Media