ADVANCED PHYSICAL DESIGN

Job oriented Training + Industrial Guidance + Placement Assistance

Dive deep into physical design and shape the backbone of cutting-edge semiconductor technology and get ready for the industry

Course Features

Structured Course Curriculum

Comprehensive learning path designed by industry experts

24/7 Industry Tool Access

Access to professional tools anytime for practical learning

Mock Interview Preparation

Personalized coaching to ace technical interviews

Best Live Sessions

Interactive sessions with experienced instructors

Industrial Project Assistance

Guidance on real-world projects for portfolio building

1:1 Mentorship

Personalized guidance from industry professionals

Resume Preparation

Professional resume building tailored to verification roles

Placement Guaranteed

Job placement assistance with our industry partners

Course Modules

Module 1 - Advanced Digital Logic Design

Introduction to VLSI

ASIC vs FPGA vs System on chip Design

Digital Logic Design - All Basic topics

Logic gates, Boolean Algebra, K-maps

All types of Combinational Circuits

All type of Sequential Circuits

Shift Registers

Counters

FSMs and Its Application examples

Static Timing Analysis

CMOS Logic Design

Glitches & Hazards

Interview Preparation

Regular Assignments

Mocktests

Interview Preparation

Module 2 - RTL Design using Verilog HDL

Language Basics and Applications

Data Types, Operators, and Syntax

All Description Styles – Theory explanation

Behavioral Modeling

Dataflow Modelling - Lab sessions

Gate Level Modelling - Lab sessions

Switch Level Modelling - Lab sessions

Types of Procedural Statements

Types of Continuous Statements

Blocking and Non-Blocking Assignments - Lab Sessions

Introducing the Process of Synthesis

Coding RTL for Synthesis

Modelling of Combinational Circuits, Latches, Flipflop, Registers, Counters

Registers, Counters

Regular Assignments, Mock Tests

Interview Preparation

Module 3 - Physical Design Flow

Overview of Advanced Physical Design

Floor Planning and Power Planning

Placement

Clock Tree Synthesis (CTS)

Routing

Timing and Signal Integrity

Power and Thermal Analysis

Design for Manufacturability (DFM)

Physical Verification

Module 4 - Linux, TCL, TK Scripting

Fundamentals of TCL Scripting

Variables, Loops, and Conditionals

Procedures and Functions

TCL in EDA Tools

Automating Placement and Routing Tasks

Debugging and Design Rule Checks

Real-World Applications of TCL

Optimization Scripts for Design Closure

Lab: Writing and Deploying TCL Scripts in Physical Design

Module 5 - RTL to GDSII (DFM)

End-to-End RTL-to-GDSII Flow

Implement Synthesis, DFT, and Physical Design

Basics of DFT

DFT Insertion

Scan Chain Design and Insertion

Boundary Scan (JTAG) Basics

Built-In Self-Test (BIST) Techniques

Hands-On: Implement Scan Chains and ATPG

Module 6 - Overview of Advanced Physical Design

VLSI Backend Design Flow

Advanced Technology Nodes (7nm, 5nm, 3nm, etc.)

Foundry and Process Design Kits (PDK)

Case Study: Advanced Nodes in Real-World Designs

Module 7 - Floor Planning and Power Planning

Advanced Floor Planning Strategies

Macro Placement Optimization

Pin and IO Placement

Hierarchical vs. Flat Floor Planning

Advanced Power Grid Design

Dynamic Power Analysis

Low-Power Techniques (Dynamic Voltage Scaling, Multi-Vt)

Case Study: Power Planning for High-Performance Chips

Module 8 - Physical Verification

Advanced LVS and DRC Techniques

Parasitic Extraction and Post-Layout Simulation

Physical Verification for FinFET and 3D ICs

Signoff Tools and Methodologies

Lab: Physical Verification of an Advanced Node Design

Projects & Protocols

Project 1 - UART Protocol - RTL Design Using Verilog HDL

Theory

Introduction to UART Protocol: Features and Applications
Functional Block Diagram of UART
Signal Definitions and Timing Diagram

Implementation

Transmitter Design: FSM Implementation, Baud Rate Generator
Receiver Design: FSM Implementation, Data Sampling
RTL Coding of UART Transmitter and Receiver using Verilog HDL
Testbench Creation and Simulation
Debugging and Waveform Analysis

Project 2 - Based on Area of Interest

Theory

Fundamentals of SoC Design Methodologies
RTL-to-GDSII Design Flow Concepts
Power Integrity and Noise Analysis Techniques

Implementation

High-Performance Processor Floorplan and Power Grid Design
Low-Power Multi-Core SoC Design
SRAM Design and Physical Implementation
Design RTL-to-GDSII Implementation
Advanced Routing Optimization for 3nm Design
Advanced Power Integrity Analysis

Project 3 - AMBA Protocols

Theory

Deep Dive into AMBA Protocols: Overview and Features
Detailed Signal Features of APB, AHB, and AXI Protocols
Comparison and Use Cases in Industry

Implementation

APB Protocol: RTL Design and Verification using SystemVerilog
AHB Protocol: RTL Design and UVM-Based Verification
AXI Protocol: Advanced RTL Design and UVM-Based Verification
Developing Comprehensive Test Plans and Writing Test Cases
Debugging and Coverage Analysis for AMBA Protocols

Project 4 - Port Calculator

Theory

Functional Overview and Applications

Implementation

RTL Design of 4-Port Calculator
UVM Testbench Development for Verification
Test Cases and Coverage Analysis

Project 5 - 1x3 Router

Theory

Router Design: Basics and Functionality

Implementation

RTL Design of 1x3 Router
Writing Test Cases in UVM
Verification and Debugging

Project 6 - DMA Controller

Theory

Overview of DMA Controller: Functionality and Applications

Implementation

RTL Design of DMA Controller
Test Plan Development and Test Case Writing
Verification using UVM and Coverage Analysis

System on Chip Design

Introduction to System on Chip Design

SOC Verification vs IP Verification

Verification approaches at Industry level

Pre silicon vs Post silicon Verification

Verification vs Validation

ADVANCED PHYSICAL DESIGN

Course Features

Structured Course Curriculum

24/7 Industry Tool Access

Mock Interview Preparation

Best Live Sessions

Industrial Project Assistance

1:1 Mentorship

Resume Preparation

Placement Guaranteed

Course Modules

Module 1 - Advanced Digital Logic Design

Module 2 - RTL Design using Verilog HDL

Module 3 - Physical Design Flow

Module 4 - Linux, TCL, TK Scripting

Module 5 - RTL to GDSII (DFM)

Module 6 - Overview of Advanced Physical Design

Module 7 - Floor Planning and Power Planning

Module 8 - Physical Verification

Projects & Protocols

Project 1 - UART Protocol - RTL Design Using Verilog HDL

Theory

Implementation

Project 2 - Based on Area of Interest

Theory

Implementation

Project 3 - AMBA Protocols

Theory

Implementation

Project 4 - Port Calculator

Theory

Implementation

Project 5 - 1x3 Router

Theory

Implementation

Project 6 - DMA Controller

Theory

Implementation

System on Chip Design

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