ADVANCED PHYSICAL DESIGN

Job oriented Training + Industrial Guidance + Placement Assistance

Dive deep into physical design and shape the backbone of cutting-edge semiconductor technology and get ready for the industry

Course Features

Structured Course Curriculum

Comprehensive learning path designed by industry experts

24/7 Industry Tool Access

Access to professional tools anytime for practical learning

Mock Interview Preparation

Personalized coaching to ace technical interviews

Best Live Sessions

Interactive sessions with experienced instructors

Industrial Project Assistance

Guidance on real-world projects for portfolio building

1:1 Mentorship

Personalized guidance from industry professionals

Resume Preparation

Professional resume building tailored to verification roles

Placement Guaranteed

Job placement assistance with our industry partners

What skills will you be learning in the next six months?

A comprehensive learning journey designed to transform you into a Physical Design expert

Module 0 - Introduction to VLSI

Foundation

Lay the groundwork with fundamental VLSI concepts and industry overview

VLSI Design Flow Overview
Frontend vs Backend Domains
Industry Requirements & Trends
Moore's Law & Nanometer Technology

Module 1 - Advanced Digital Logic Design

3 Weeks

Master the fundamentals of digital circuit design

Number Systems & Conversions
Combinational & Sequential Circuits
FSMs & Memory Design
Static Timing Analysis
CMOS Logic Design

Module 2 - RTL Design using Verilog HDL

1.5 Month

Become proficient in hardware description languages

Verilog HDL Fundamentals
RTL for Synthesis
Testbench Development
FIFO, RAM, ROM Design
Computer Architecture

Module 3 - Physical Design Flow

3 Months

Deep dive into complete physical design implementation

Floor Planning & Power Planning
Placement & Clock Tree Synthesis
Routing & Timing Analysis
Physical Verification
Advanced Technology Nodes (7nm, 5nm, 3nm)

Module 4 - Linux & TCL/Tk Scripting

2 Weeks

Essential scripting skills for EDA tool automation

Linux Environment & Commands
TCL Scripting Fundamentals
EDA Tool Automation
Version Control with Git

Module 5 - RTL to GDSII Flow

2 Weeks

End-to-end implementation flow mastery

Complete RTL to GDSII Flow
DFT Insertion Concepts
Signoff Methodologies
Industry Standard Practices

Module 6 - Projects & Protocols

1 Month

Hands-on experience with real-world projects

UART, I2C, AMBA Protocols
RISC-V Core Implementation
Router & Pipeline Designs
Capstone Project

Module 7 - SOC Level Design

1 Week

System-level design understanding

SOC Architecture
IP Integration
System Verification
Industry SOC Methodologies

Module 8 - Career Preparation

1 Month

Final preparation for industry placement

Aptitude & Logical Reasoning
Communication Skills
Mock Interviews
Comprehensive Revision
1:1 Mentorship Sessions

Industry Standard Tools Access

Get hands-on experience with professional EDA tools

Siemens

Tanner, Calibre

Synopsys

Design Compiler, IC Compiler

Xilinx

Vivado, ISE

Cadence

Innovus, Genus, Virtuoso

Course Modules

Introduction to VLSI Design

Overview of VLSI Design Flow

Frontend Domain vs Backend Domain

Discussion on Industry Requirements

Moore Law, Nano meter technology

FPGA vs ASIC vs SOC designs

SOC vs Subsystem vs IP level Verification

Future of VLSI, What next big thing in VLSI ?

Importance of Digital electronics

Introduction to RTL Design & Verification

Module 1 - Advanced Digital Logic Design

All concepts from scratch

Number systems, Conversions

Logic gates, Universal gates

Boolean Algebra, K-maps

All type of Combinational logic circuits

All type of Sequential logic circuits

Shift Registers

Counters designs

FSMs and Its Application examples

Memories

Static Timing Analysis

CMOS Logic Design

Glitches & Hazards

Interview Preparation Regular Assignments

Mock tests Interview Preparation

Module 2 - RTL Design using Verilog HDL

Verilog HDL vs VHDL

Language Introduction and Applications

Data types, Operators

All Description Styles

Theory explanation Behavioral Modelling - Lab sessions

Dataflow Modelling - Lab sessions

Gate Level Modelling - Lab sessions

Switch Level Modelling - Lab sessions

Types of Procedural Statements

Types of Continuous Statements

Blocking and Non-Blocking Assignments - Lab Sessions

Introducing the Process of Synthesis Coding

RTL for Synthesis Modelling of Combinational Circuits

Adders, Subtractors, Ripple carry adder

Mux, Demux, Hierarchy models, Encoders, decoders

Latches, Flipflop, Registers

Counters RTL Design

FSMs & Memories

RTL Design and Verification of FIFO | RAM | RO

Testbench concepts for Verification from Basics to PRO

Verilog 1 week Challenge, Logical problem solving

Extra projects & Computer Architecture

Regular Assignments

Mock Tests

Interview Preparation

Module 3 - Physical Design Flow

Overview of Advanced Physical Design

Floor planning and Power Planning

Placement

Clock Tree Synthesis (CTS)

Routing

Timing and Signal Integrity

Power and Thermal Analysis

Design for Manufacturability (DFM)

Physical Verification

VLSI Backend Design Flow

Advanced Technology Nodes (7nm, 5nm, 3nm, etc.)

Challenges in Modern Physical Design

Foundry and Process Design Kits (PDK)

Case Study: Advanced Nodes in Real-World Designs

Floor Planning and Power Planning

Advanced Floorplanning Strategies

Macro Placement Optimization

Pin and IO Placement

Hierarchical vs. Flat Floorplanning

Advanced Power Grid Design

Dynamic Power Analysis

Low-Power Techniques (Dynamic Voltage Scaling, Multi-Vt)

Case Study: Power Planning for High-Performance Chips

Placement

Timing-Driven Placement

Congestion Estimation and Mitigation

Machine Learning Techniques in Placement Optimization

Multi-Die Placement in 3D ICs

Density Optimization and Design Closure

Lab: Placement Optimization Using Industry Tools

Clock Tree Synthesis (CTS)

Advanced Clock Tree Design

Low-Skew and Low-Latency Clock Trees

Mesh vs. H-Tree vs. Clock Gating

Clock Domain Crossing (CDC) Challenges

Multi-Corner Multi-Mode (MCMM) CTS Techniques

Power-Aware CTS

Lab: Advanced CTS Implementation in EDA Tools

Routing

Advanced Routing Techniques

Routing Challenges at Advanced Nodes

Crosstalk and RC Delay Optimization

Detailed Routing Optimization

DFM-Aware Routing

Lab: Routing Optimization in EDA Tools

Timing and Signal Integrity

Advanced Static Timing Analysis (STA)

Multi-Mode Multi-Corner Analysis

Path-Based Analysis (PBA)

Clock Skew, Jitter, and Timing Closure

Signal Integrity Challenges and Mitigation

Lab: Timing Optimization and SI Analysis

Power and Thermal Analysis

Advanced IR Drop Analysis

Power Grid Optimization at Advanced Nodes

Thermal Analysis and Hotspot Mitigation

Electrostatic Discharge (ESD) Protection

Lab: Power and Thermal Analysis with Signoff Tools

Physical Verification

Advanced LVS and DRC Techniques

Parasitic Extraction and Post-Layout Simulation

Physical Verification for FinFET and 3D ICs

Signoff Tools and Methodologies

Lab: Physical Verification of an Advanced Node Design

Module 4 -TCL Scripting

Introduction to TCL

Substitution and Data Types

Fundamentals of TCL Scripting

Variables, Loops, and Conditionals

Procedures and Functions

TCL in EDA Tools

Operators and Decision Making

Loops and Arrays

String and List Handling

Procedures and Functions

File Handling and Regular Expressions

Application-oriented TCL Scripting - Floorplan, Placement, Routing, Clock Tree Synthesis (CTS)

Introduction to Linux Essential

Linux Commands Text Editors

Shell Scripting Environment

Setup Version Control with Git

Module 5 -RTL to GDSII Flow Projects

Protocol 1 - UART Protocol - RTL Design Using Verilog HDL

Theory

Introduction to UART Protocol: Features and Applications

Functional Block Diagram of UART

Signal Definitions and Timing Diagram

Implementation

PD Flow design - RTL to GDS

Protocol 2 - I2C Protocol Implementation and Verification

Theory

I2C Protocol Overview: Features, Signals, and Modes of Operation

Multi-Master and Multi-Slave Configurations

Timing Diagram and Bit-Level Analysis

Implementation

PD Flow design - RTL to GDS

Protocol 3 - AMBA APB AHB AXI

Theory

Deep into Specification Explanation

Features of Bus Protocols

Pipeline & Non-Pipeline Structure

Detailed Understanding on Master & Slave Transactions

Module 6 - Projects & Protocols

3 Major Projects - Selective Projects

Capstone Project

Physical Design & Implementation on RISC-V Core Design

Physical Verification of RISC-V Design

Router 1x3 Block Level Physical Design

Pipeline Design (Adder / Multiplier)

System on Chip Design

Introduction to System on Chip Design

SOC Verification vs IP Verification

Verification approaches at Industry level

Pre silicon vs Post silicon Verification

Verification vs Validation

ADVANCED PHYSICAL DESIGN

Course Features

Structured Course Curriculum

24/7 Industry Tool Access

Mock Interview Preparation

Best Live Sessions

Industrial Project Assistance

1:1 Mentorship

Resume Preparation

Placement Guaranteed

What skills will you be learning in the next six months?

Module 0 - Introduction to VLSI

Module 1 - Advanced Digital Logic Design

Module 2 - RTL Design using Verilog HDL

Module 3 - Physical Design Flow

Module 4 - Linux & TCL/Tk Scripting

Module 5 - RTL to GDSII Flow

Module 6 - Projects & Protocols

Module 7 - SOC Level Design

Module 8 - Career Preparation

Industry Standard Tools Access

Siemens

Synopsys

Xilinx

Cadence

Course Modules

Introduction to VLSI Design

Module 1 - Advanced Digital Logic Design

Module 2 - RTL Design using Verilog HDL

Module 3 - Physical Design Flow

Module 4 -TCL Scripting

Module 5 -RTL to GDSII Flow Projects

Module 6 - Projects & Protocols

System on Chip Design

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