RTL Design and DFT Internship

Job oriented Training + Industrial Guidance + Placement Assistance

"Enhance your skills in RTL Design and Design for Testability (DFT) with practical, project-based industrial training."

Course Module

Module 1 - Advanced Digital Logic Design

Introduction to VLSI

ASIC vs FPGA vs System on chip Design

Digital Logic Design - All Basic topics

Logic gates, Boolean Algebra, K-maps

All types of Combinational Circuits

All type of Sequential Circuits

Shift Registers

Counters

FSMs and Its Application examples

Static Timing Analysis

CMOS Logic Design

Glitches & Hazards

Interview Preparation

Regular Assignments

Mocktests

Interview Preparation

Module 2 - RTL Design using Verilog HDL

Language Basics and Applications

Data Types, Operators, and Syntax

All Description Styles – Theory explanation

Behavioral Modeling

Dataflow Modelling - Lab sessions

Gate Level Modelling - Lab sessions

Switch Level Modelling - Lab sessions

Types of Procedural Statements

Types of Continuous Statements

Blocking and Non-Blocking Assignments - Lab Sessions

Introducing the Process of Synthesis

Coding RTL for Synthesis

Modelling of Combinational Circuits, Latches, Flipflop, Registers, Counters

Registers, Counters

Regular Assignments, Mock Tests

Interview Preparation

Module 3 - Perl Scripting

Introduction to Linux Setup

Importance of Perl Scripting

How to run the commands

Idea on Coverage analysis

Upload and extract the coverage report

Walk through Perl concepts

Coding standards

Explanation of Data types, Arrays

Hashes, Loops

Operators, Subroutines

Date & Time

References, Formats

Directories

Error Handling

Design for Testability

Module 1 - Introduction to Design for Testability

Importance of Testing in VLSI Design
Overview of Manufacturing Defects and Fault Models
Stuck-at Faults
Transition Faults
Bridge Faults
Open Faults
Yield, Reliability, and Cost Considerations
Basics of Testing
Functional Testing
Structural Testing
Logical vs. Physical Testing

Module 2 - Design for Testability Techniques

Ad Hoc DFT Techniques
Structured DFT Techniques
Scan Design
Built-In Self-Test (BIST)
Boundary Scan (IEEE 1149.1, JTAG)
Controllability and Observability Metrics (SCOAP)

Module 3 - Scan-Based Testing

Introduction to Scan Design
Types of Scan Architectures
MUXed Scan
LSSD (Level-Sensitive Scan Design)
Enhanced Scan
Scan Chain Implementation and Insertion
Scan Chain Faults and Debugging
Low Power Testing in Scan Design

Module 4 - Built-In Self-Test (BIST)

Introduction to BIST
BIST Architectures
Test Pattern Generators (TPG)
Output Response Analyzers (ORA)
Linear Feedback Shift Registers (LFSR)
Memory BIST (MBIST)
March C-, March Y Algorithms
Logic BIST (LBIST)
Signature Analysis, PRBS Generation

Module 5 - Boundary Scan and JTAG

Boundary Scan Basics
IEEE 1149.1 Standard
TAP Controller and Instruction Register
Boundary Scan Chain Design
Debugging and In-System Testing using JTAG

Module 6 - Advanced DFT Concepts

Advanced Fault Models
Delay, Bridging, Crosstalk Faults
DFT for Low Power Designs
Test Compression Techniques
X-Handling in ATPG, Test Point Insertion
DFT Challenges in Multi-Voltage/Clock Designs
Fault Diagnosis and Debugging Techniques

Module 7 - Physical Design Considerations for DFT

DFT and Physical Design Flow Integration
Clock Domain Crossing (CDC) in DFT
Routing and Placement Challenges for DFT
DFT for 3D ICs and TSV-Based Designs

Module 8 - DFT Tools and Industry Practices

Popular DFT Tools
Synopsys (DFT Compiler, Tetramax)
Cadence (Modus)
Mentor (Tessent)
DFT Flow Automation
Test Data Management
Industry Protocols and Standards

Module 9 - Advanced Applications and Case Studies

Scan Chain Implementation and ATPG Flow
Memory BIST Design and Verification
Logic BIST Implementation
Fault Simulation and Coverage Analysis
Real-World Case Studies in Industry
DFT for AI/ML Accelerators and Advanced SoCs

Projects & Protocol

Project 1 - UART Protocol - RTL Design Using Verilog HDL

Theory

Introduction to UART Protocol: Features and Applications
Functional Block Diagram of UART
Signal Definitions and Timing Diagram

Implementation

Transmitter Design: FSM Implementation, Baud Rate Generator
Receiver Design: FSM Implementation, Data Sampling
RTL Coding of UART Transmitter and Receiver using Verilog HDL
Testbench Creation and Simulation
Debugging and Waveform Analysis

Project 2 - I2C Protocol Implementation and Verification

Theory

I2C Protocol Overview: Features, Signals, and Modes of Operation
Multi-Master and Multi-Slave Configurations
Timing Diagram and Bit-Level Analysis

Implementation

RTL Design of I2C Controller
Writing Test Cases in SystemVerilog
Testbench Creation and Verification using SystemVerilog
Coverage Metrics and Analysis

Project 3 - AMBA Protocols (APB, AHB, AXI)

Theory

Deep Dive into AMBA Protocols: Overview and Features
Detailed Signal Features of APB, AHB, and AXI Protocols
Comparison and Use Cases in Industry

Implementation

APB Protocol: RTL Design and Verification using SystemVerilog
AHB Protocol: RTL Design and UVM-Based Verification
AXI Protocol: Advanced RTL Design and UVM-Based Verification
Developing Comprehensive Test Plans and Writing Test Cases
Debugging and Coverage Analysis for AMBA Protocols

Project 4 - 4-Port Calculator

Theory

Functional Overview and Applications

Implementation

RTL Design of 4-Port Calculator
UVM Testbench Development for Verification
Test Cases and Coverage Analysis

Project 5 - 1x3 Router

Theory

Router Design: Basics and Functionality

Implementation

RTL Design of 1x3 Router
Writing Test Cases in UVM
Verification and Debugging

Project 6 - DMA Controller

Theory

Overview of DMA Controller: Functionality and Applications

Implementation

RTL Design of DMA Controller
Test Plan Development and Test Case Writing
Verification using UVM and Coverage Analysis

System on Chip Design

Introduction to System on Chip Design

SOC Verification vs IP Verification

Verification approaches at Industry level

Pre silicon vs Post silicon Verification

Verification vs Validation

RTL Design and DFT Internship

Course Module

Module 1 - Advanced Digital Logic Design

Module 2 - RTL Design using Verilog HDL

Module 3 - Perl Scripting

Design for Testability

Module 1 - Introduction to Design for Testability

Module 2 - Design for Testability Techniques

Module 3 - Scan-Based Testing

Module 4 - Built-In Self-Test (BIST)

Module 5 - Boundary Scan and JTAG

Module 6 - Advanced DFT Concepts

Module 7 - Physical Design Considerations for DFT

Module 8 - DFT Tools and Industry Practices

Module 9 - Advanced Applications and Case Studies

Projects & Protocol

Project 1 - UART Protocol - RTL Design Using Verilog HDL

Theory

Implementation

Project 2 - I2C Protocol Implementation and Verification

Theory

Implementation

Project 3 - AMBA Protocols (APB, AHB, AXI)

Theory

Implementation

Project 4 - 4-Port Calculator

Theory

Implementation

Project 5 - 1x3 Router

Theory

Implementation

Project 6 - DMA Controller

Theory

Implementation

System on Chip Design

Courses

Company

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