Advanced Verification Course

Job oriented Training + Industrial Guidance + Placement Assistance

Master the art of functional verification with Advanced Coverage techniques and build a career in chip design with hands-on UVM expertise

Course Features

Structured Course Curriculum

Comprehensive learning path designed by industry experts

24/7 Industry Tool Access

Access to professional tools anytime for practical learning

Mock Interview Preparation

Personalized coaching to ace technical interviews

Best Live Sessions

Interactive sessions with experienced instructors

Industrial Project Assistance

Guidance on real-world projects for portfolio building

1:1 Mentorship

Personalized guidance from industry professionals

Resume Preparation

Professional resume building tailored to verification roles

Placement Guaranteed

Job placement assistance with our industry partners

Course Modules

Module 1 - Revision of DLD & Verilog HDL

Interview Questions Discussion

Drawbacks of Verilog HDL

Introduction to Systemverilog

Advantages and Features of Systemverilog

Module 2 - System on Chip Design

Introduction to System on Chip Design

SOC Verification vs IP Verification

Verification approaches at Industry level

Pre silicon vs Post silicon Verification

Verification vs Validation

Module 3 - Verification using SystemVerilog

SystemVerilog Overview

Standard Data types & Literals & Operators

User-Defined Data types & Structures

Tb Architecture & Connectivity

Static, Dynamic, Associative Arrays

Queues

Tasks & Functions

Interfaces, Virtual Interface Verification Features

Polymorphism and Virtuality

Class-Based Random Stimulus

Direct Programming Interface(DPI)

Testplans, Testcases

All topics theory + Lab sessions

Regular assignments

Mock tests

Interview Preparation

Module 4 - Verification using UVM

Deep understanding of UVM in SOC | IP

Detailed explanation on UVC in SOC | IP

Introduction to UVM, Features

Testbench Hierarchy, Components

UVM Sequence Item, Sequence, Sequencer

Configuration, UVM config_db

UVM Phases

UVM Driver

UVM Monitor

UVM Agent

UVM Scoreboard

UVM Environment

Creating all components in a flow

Understanding of UVM RAL Model

UVM Testbench Examples

Interview Preparation

Module 5 - Perl Scripting

Introduction to Linux Setup

Importance of Perl Scripting

How to run the commands

Idea on Coverage analysis

Upload and extract the coverage report

Walk through perl concepts

Coding standards

Explanation of Data types, Arrays

Hashes, Loops

Operators, Subroutines

Date & Time

References, Formats

Directories

Error Handling

Module 6 - 6 Industrial Protocols, 3 Major Projects

Protocols & Projects

Protocol 1 - UART (RTL Design & Verification)

Protocol 2 - I2C (RTL Design & SV Verification)

Protocol 3 - AMBA APB, AHB, AXI (VIP Development)

AHB to APB Bridge (RTL Design & Verification)

Protocol 4 - PCIe Gen 3 to Gen 6

Protocol 5 - Ethernet (10G/40G/100G)

Ethernet MAC & PHY Layer
Packet Transmission & Reception
Verification of High-Speed Interfaces

Protocol 6 - SPI & CAN (RTL Design & Verification)

Serial Peripheral Interface (SPI) – Master/Slave
CAN Protocol – Controller Area Network for Automotive
RTL Design & SystemVerilog Verification

Project 1 - RISC V Processor (RTL Design & SV Verification)

Week 7: RISC-V Basics & Single-Cycle Implementation

ISA Basics, ALU, Control Unit, Memory Interface
Pipeline Stages Overview (IF, ID, EX, MEM, WB)
Single-Cycle RISC-V CPU in Verilog

Week 8: Pipelined RISC-V Design & Verification

5-Stage Pipeline, Hazard Handling (Stalls, Forwarding)
Verilog RTL for Each Stage & Integration
SystemVerilog Testbench, Assertions, Coverage

Project Goal: Design & Verify a Pipelined RISC-V CPU

Project 2 - DDR2 to DDR5 Controller (RTL Design & Verification)

Introduction

DDR Evolution: DDR2 → DDR5
Applications, Architecture, Timing Parameters

Week 10: RTL & Verification

Command Decoder, Bank Management, Address Mapping
SystemVerilog Memory Model, Assertions, Coverage

Project Goal: RTL Design & Verification of Simplified DDR Controller

Project 3 - 1x3 Router (UVM Verification)

Theory

Router Basics: Role in SoC & NoC, Packet Structure
1x3 Router Architecture: FSM, Synchronizer, Registers, FIFOs

RTL Design

FSM-based Flow Control, Synchronizers, FIFO Buffers

UVM Verification

Sequence, Driver, Monitor, Scoreboard
Coverage & Functional Testcases

Project Goal: Design & Verify Router using UVM

System on Chip Design