Advanced Verification Internship

Job oriented Training + Industrial Guidance + Placement Assistance

Dive deep into advanced ASIC verification techniques with Systemverilog, UVM and industry protocols, guided by expert mentors.

Course Module

Module 1 - Revision of DLD & Verilog HDL

Interview Questions Discussion

Drawbacks of Verilog HDL

Introduction to Systemverilog

Advantages and Features of Systemverilog

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Module 3 - Verification using SystemVerilog

SystemVerilog Overview

User-Defined Data types & Structures

Static, Dynamic, Associative Arrays

Tasks & Functions

Interfaces & Virtual Interfaces

Clocking Blocks, Modports

OOPs Concepts: Classes & Inheritance

Polymorphism and Encapsulation

Random Stimulus Generation

SystemVerilog Assertions (SVA)

Functional & Toggle Coverage

Assertion Based Verification (ABV)

Testbench Architecture & Components

Testplans & Testcases

Module 4 - Verification using UVM

Introduction to UVM & its Features

Testbench Hierarchy and UVM Components

UVM Sequence Item, Sequence, Sequencer

Configuration Database (config_db)

UVM Phases and Transaction Flow

Driver, Monitor, Agent & Environment

UVM Scoreboard and Analysis Ports

Creating Complete UVM Testbench Flow

Understanding UVM RAL Model

Deep Dive into UVM TLM Communication

Testplan and Testcase Scenario Design

Running Regressions and Result Analysis

Debugging Techniques for SOC/IP Level

Theory + Lab Sessions with Real Examples

Mock Tests & Interview Preparation

Module 5 - Perl Scripting

Introduction to Linux Setup

Importance of Perl Scripting

How to Run the Commands

Idea on Coverage Analysis

Upload and Extract the Coverage Report

Walk Through Perl Concepts

Coding Standards

Explanation of Data Types, Arrays

Hashes and Loops

Operators and Subroutines

Date & Time Handling

References and Formats

Working with Directories

Error Handling in Perl

Projects & Protocols

Project 1 - UART Protocol - RTL Design Using Verilog HDL

Theory

Introduction to UART Protocol: Features and Applications
Functional Block Diagram of UART
Signal Definitions and Timing Diagram

Implementation

Transmitter Design: FSM Implementation, Baud Rate Generator
Receiver Design: FSM Implementation, Data Sampling
RTL Coding of UART Transmitter and Receiver using Verilog HDL
Testbench Creation and Simulation
Debugging and Waveform Analysis

Project 2 - I2C Protocol Implementation and Verification

Theory

I2C Protocol Overview: Features, Signals, and Modes of Operation
Multi-Master and Multi-Slave Configurations
Timing Diagram and Bit-Level Analysis

Implementation

RTL Design of I2C Controller
Writing Test Cases in SystemVerilog
Testbench Creation and Verification using SystemVerilog
Coverage Metrics and Analysis

Project 3 - AMBA Protocols (APB, AHB, AXI)

Theory

Deep Dive into AMBA Protocols: Overview and Features
Detailed Signal Features of APB, AHB, and AXI Protocols
Comparison and Use Cases in Industry

Implementation

APB Protocol: RTL Design and Verification using SystemVerilog
AHB Protocol: RTL Design and UVM-Based Verification
AXI Protocol: Advanced RTL Design and UVM-Based Verification
Developing Comprehensive Test Plans and Writing Test Cases
Debugging and Coverage Analysis for AMBA Protocols

Project 4 - 4-Port Calculator

Theory

Functional Overview and Applications

Implementation

RTL Design of 4-Port Calculator
UVM Testbench Development for Verification
Test Cases and Coverage Analysis

Project 5 - 1x3 Router

Theory

Router Design: Basics and Functionality

Implementation

RTL Design of 1x3 Router
Writing Test Cases in UVM
Verification and Debugging

Project 6 - DMA Controller

Theory

Overview of DMA Controller: Functionality and Applications

Implementation

RTL Design of DMA Controller
Test Plan Development and Test Case Writing
Verification using UVM and Coverage Analysis

System on Chip Design

Introduction to System on Chip Design

SOC Verification vs IP Verification

Verification approaches at Industry level

Pre silicon vs Post silicon Verification

Verification vs Validation

Advanced Verification Internship

Course Module

Module 1 - Revision of DLD & Verilog HDL

Module 3 - Verification using SystemVerilog

Module 4 - Verification using UVM

Module 5 - Perl Scripting

Projects & Protocols

Project 1 - UART Protocol - RTL Design Using Verilog HDL

Theory

Implementation

Project 2 - I2C Protocol Implementation and Verification

Theory

Implementation

Project 3 - AMBA Protocols (APB, AHB, AXI)

Theory

Implementation

Project 4 - 4-Port Calculator

Theory

Implementation

Project 5 - 1x3 Router

Theory

Implementation

Project 6 - DMA Controller

Theory

Implementation

System on Chip Design

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