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Verification using UVM

"Enhance your debugging expertise and verification proficiency with Universal Verification Methodology skills & deep into writing test benches." Learn more

Course Modules

Module 1 - Introduction to UVM

Topics

  • What is UVM and Why is it Important?
  • Features and Benefits of UVM in Design Verification
  • UVM vs. Traditional Verification Approaches
  • UVM Libraries and Simulation Tools

Features

  • Live Sessions with hands-on demonstration of UVM basics.
  • Exercises to set up a UVM environment.

Module 2 - UVM Components and Hierarchy

Topics

  • Overview of UVM Testbench Architecture
  • UVM Components: Driver, Monitor, Agent, Scoreboard, Environment, Test
  • Creating and Connecting Components in a Flow

Features

  • Hands-on labs for designing and instantiating UVM components.
  • Debugging sessions for typical issues in UVM environments.

Module 3 - UVM Sequence and Configuration

Topics

  • UVM Sequence Items, Sequences, and Sequencers
  • Configuration Mechanism (uvm_config_db)
  • UVM Phases and Execution Flow
  • Sequence Control and Advanced Sequencer Features

Features

  • Practical assignments for creating sequences and configuring UVM tests.
  • Examples of parameterized sequences.

Module 4 - Advanced UVM Topics

Topics

  • UVM TLM (Transaction-Level Modeling) Interfaces
  • Callbacks and Events in UVM
  • UVM Register Abstraction Layer (RAL) Model
  • UVM Debugging: Common Errors and Their Fixes
  • Integrating UVM with Regression Suites

Features

  • Debugging assignments for callback and TLM use cases.
  • Developing reusable verification environments.

Module 5 - Test Planning and Coverage

Topics

  • Creating a UVM Testplan
  • Detailed Test Plan Explanation (DTP)
  • Writing Testcases for Functional and Protocol Verification
  • Importance of Regression Testing
  • Analyzing Functional Coverage in UVM

Features

  • Hands-on lab for writing detailed test plans.
  • Examples of functional and code coverage analysis.

Module 6 - UVM Reporting, Messaging, and Utilities

Topics

  • UVM Reporting Mechanism: uvm_info, uvm_warning, uvm_error, uvm_fatal
  • Controlling Verbosity and Message Output
  • UVM Macros and Utility Methods
  • Factory Mechanism and Overrides
  • Resource Management in UVM

Features

  • Live demonstrations on customizing UVM reports and messages.
  • Exercises using factory overrides and resource configuration.
  • Debugging sessions with UVM utilities and message control.

UVM Reporting, Messaging, and Utilities

Protocol Design and Verification

AHB Protocol

Objective
  • RTL Design and UVM Verification of AMBA AHB
Design
  • Implement AHB Master and Slave
  • Support Transfer Types and Burst Modes
  • Error Detection and Reporting
Verification
  • UVM-Based Testbench Development
  • Randomized Testcases for Edge Scenarios
Coverage
  • Functional Coverage of AHB Transactions
  • Assertions for Protocol Adherence

AXI Protocol

Objective
  • RTL Design and UVM Verification of AMBA AXI
Design
  • AXI Master and Slave RTL Implementation
  • Support Read/Write Channels & Burst Transactions
  • Handle Out-of-Order Operations
Verification
  • Develop UVM-Based Testbench
  • Transaction-Level Modeling for AXI
Coverage
  • Cross-Coverage for Multi-Master/Slave Systems
  • Assertion-Based Verification of AXI Specs

Project Card

Projects - Minor Project: Router Design

Objective

  • Design a 1x3 Router RTL and verify it using UVM.

Workflow

  • Design: RTL implementation of a router handling packet switching.
  • Logic for routing based on header information.
  • Verification: Develop a UVM environment for router testing.
  • Write randomized and directed testcases.

Expected Outcomes

  • Functional verification of router operations.
  • Coverage metrics for router functionality.

Projects - Minor Project: 1x3 Router Design using UVM

Objective

  • Design and verify a 1x3 packet-based router using Verilog RTL and UVM.

Design

  • Develop RTL for a router handling dynamic packet switching.
  • Implement routing logic based on header decoding.

Verification

  • Create a UVM-based verification environment for the router.
  • Write randomized and directed testcases for different routing scenarios.

Expected Outcomes

  • Accurate functional verification of routing paths.
  • Measurement of functional and code coverage for verification completeness.

Additional Features

Introduction to System on Chip Design
SOC Verification vs IP Verification
Verification approaches at Industry level
Pre silicon vs Post silicon Verification
Verification vs Validation
ProVLogic

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