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Verification using Systemverilog

Master essential verification skills with a focus on real-time problem-solving with Advanced Systemverilog and Functional coverage with Assertion based verification

Course Features

Module 1 - Basics of SystemVerilog

Topics Covered

SystemVerilog Overview
  • Evolution of SystemVerilog: From Verilog to SV
  • Applications in Design and Verification
  • Enhancements Over Verilog
Data Types
  • Bit, Logic, Reg — Differences
  • typedef, enum, struct
  • Packed vs Unpacked Arrays
Control Flow & Operators
  • if-else, case, unique case
  • for, while, do-while, foreach
  • All types of operators
Arrays & Queues
  • Static, Dynamic, Associative
  • Queue operations: push, pop, insert, delete
Mailboxes & Semaphores
  • Blocking/Non-blocking Mailboxes
  • Counting Semaphores for resource sync
Casting & Conversion
  • Static vs Dynamic Casting
  • Implicit vs Explicit Conversion
Fork-Join & Process Control
  • fork...join_any, join_none
  • disable fork, event-based sync
Interface
  • Interface Declaration & Modport
  • Virtual Interfaces for Reusability
Program Block
  • initial vs always in testbenches
  • Simulation synchronization

Module 2 - Object-Oriented Programming (OOP) Concepts in SystemVerilog

Topics Covered

OOP Introduction
  • Why OOP in Verification?
  • Advantages in Testbench Development
Classes in SystemVerilog
  • Class Declaration and Usage
  • Objects and Object Lifecycle
  • Constructors and Destructors
Encapsulation
  • Data Members and Methods
  • Access Modifiers (local, protected, public)
  • Benefits in Testbench Design
Inheritance
  • Overriding and Extending Methods
  • Use of super Keyword
Polymorphism
  • Virtual Methods
  • Dynamic Method Dispatch
  • Abstract Classes and Interfaces
Virtual Interfaces
  • Role in Connecting DUT and Testbench
  • Virtuality and Use Cases
OOP in Verification
  • Creating Reusable and Scalable Components
  • Class-Based Drivers, Monitors, Scoreboards
Features
  • Hands-on examples and assignments
  • Debugging virtuality and inheritance

Module 3 - Randomization in SystemVerilog

Topics Covered

Introduction
  • Introduction to Randomization
  • Importance in Functional Verification
  • Randomization Constructs
Randomize Method
  • Using the randomize() Method
Constraints
  • Constraint Solving
  • Soft, Inline, Block Constraints
  • Solving Constraint Conflicts
Class-Based Randomization
  • Random Variables in Classes
  • Randomization within Objects
Advanced Techniques
  • Distribution Constraints
  • foreach Constraints
  • dist Method for Weighted Randomization
Controlling Randomization
  • Pre/Post Randomization Functions
  • Seed Control
  • Repeatability
  • Debugging Issues
Practical Use Cases
  • Random Packet Generation
  • Protocol Verification Scenarios
Features
  • Hands-on randomization coding
  • Debugging constraint conflicts

Module 4 - Functional Coverage

Topics Covered

Introduction
  • What is Functional Coverage?
  • Importance in Functional Verification
  • Types: Code, Functional, Assertions
Covergroups
  • Creating and Instantiating Covergroups
  • Coverpoints and Cross Coverage
  • Sampling Techniques
Coverage Options
  • Bins and Weighted Coverage
  • Automatic vs Manual Binning
  • Excluding Bins, Ignore Constraints
Coverage Analysis
  • Collecting Coverage Reports
  • Analyzing Results
  • Achieving 100% Functional Coverage
Advanced Topics
  • Weighted and Hierarchical Coverage
  • Coverage with Randomized Stimuli
  • Debugging Coverage
Features
  • Labs for writing/analyzing covergroups
  • Coverage reporting exercises

Module 5 - Assertions and Assertion-Based Verification (ABV)

Topics Covered

Introduction
  • What are Assertions?
  • Types: Immediate & Concurrent
  • Benefits in Functional Verification
Immediate Assertions
  • Writing and Using
  • Debugging Techniques
Concurrent Assertions
  • PSL Basics
  • Using sequence and property
  • Constructs: assert, assume, cover
SystemVerilog Assertions (SVA)
  • Writing Protocol & Functional Checks
  • Temporal Operators: ##, @, |->, |=>
Advanced Assertions
  • Verification of APB, AXI, I2C
  • Assertion Coverage
  • Debugging Failures
Assertion-Based Verification
  • ABV Methodology Overview
  • Integration into Environments
  • Improving Coverage with Assertions
Features
  • Hands-on labs for assertion writing
  • Real-world debugging assignments

Projects Modules

Projects & Protocol Implementation

Projects

Minor Project: 4-Port Calculator
  • Design Focus: Arithmetic Logic
  • Functional Verification
  • Functional Coverage Implementation
Major Project: DMA Controller
  • Design of Control Channels & Registers
  • Multiple Data Transfer Modes
  • RTL Implementation in SystemVerilog
  • Assertion-Based Verification
  • Coverage-Driven Development

Protocol Designs

I2C Protocol
  • SystemVerilog RTL: Master & Slave
  • Implement Start, Stop, Data Transfer, ACK
  • Edge Case Handling: Arbitration
I2C Verification
  • Testbench in SystemVerilog
  • Directed & Randomized Test Cases
  • SystemVerilog Assertions (SVA)
APB Interface
  • RTL Design in SystemVerilog
  • Read/Write, Address Decode, Response Logic
APB Verification
  • Reusable Testbench with OOP Concepts
  • Assertions for Timing & Compliance
Coverage Goals
  • Protocol Coverage (Valid/Invalid Cases)
  • Read/Write Operation Coverage
  • Address Alignment & Violation Checks

Course Outcomes

Fundamental Understanding

Students will gain a thorough understanding of fundamental digital logic concepts including number systems, Boolean algebra, and logic gate implementations.

Circuit Design & Analysis

Students will be able to design and analyze both combinational and sequential circuits using modern digital design methodologies.

Finite State Machines

Students will develop the skills to create Finite State Machines (FSMs) and apply them to solve complex real-world problems.

Timing & Signal Integrity

Students will understand timing constraints and signal integrity issues in digital circuits, including techniques for mitigation.

Industry Preparedness

Students will be well-prepared for technical interviews and challenges in digital logic design positions.

Additional Features

Mock Tests

Regular assessment tests to prepare you for real-world challenges and interviews.

Hands-On Assignments

Practical assignments that reinforce theoretical concepts through application.

Live Interactive Sessions

Weekly live Q&A sessions with industry experts and instructors.

Project-Based Learning

Build portfolio-ready projects that demonstrate your skills to employers.

Additional Features

Introduction to System on Chip Design
SOC Verification vs IP Verification
Verification approaches at Industry level
Pre silicon vs Post silicon Verification
Verification vs Validation
ProVLogic

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