ASIC Design & Verification

Perfect Hands on Industry Training Placement guarantee

What Skills Will You Be Learning in the Next Six Months?

Module 0

Introduction to VLSI

Module 1 3 Weeks

Advanced Digital Logic Design

Module 2 1.5 Month

RTL Design using Verilog HDL

Module 3 1.5 Month

System Verilog for Functional Verification

Module 4 1.5 Month

Universal Verification Methodology (UVM)

Module 5 1.5 Month

5 Industry Protocols (UART, I2C, APB, AHB, AXI)
3 Major Projects (RISC-V Processor, Memory Controller, Router)

Module 6 2 Weeks

Perl Scripting

Module 7 1 Week

SOC Level Verification Debugging Techniques & Methodologies

Module 8 1 Month

Aptitude & Logical Reasoning
Communication Skills Building, Mock Interviews
Revision of Digital Electronics, Verilog HDL, Physical Design Flow, TCL
Projects - 1:1 Mock

Tools Access

Xilinx, Quartus Prime, ModelSim, QuestaSim, GVim

Module 0 : Introduction to VLSI Design

Overview of VLSI Design Flow
Frontend Domain vs Backend Domain
Discussion on Industry Requirements
Moore's Law, Nanometer Technology
FPGA vs ASIC vs SoC Designs
SoC vs Subsystem vs IP Level Verification
Future of VLSI – What’s Next?
Importance of Digital Electronics
Introduction to RTL Design & Verification

Course Modules

Module 1 - Advanced Digital Logic Design

All concepts from scratch

Number systems, Conversions

Logic gates, Universal gates

Boolean Algebra, K-maps

All type of Combinational logic circuits

All type of Sequential logic circuits

Shift Registers

Counters designs

FSMs and Its Application examples

Memories

Static Timing Analysis

CMOS Logic Design

Glitches & Hazards

Interview Preparation Regular Assignments

Mock tests Interview Preparation

Module 2 - RTL Design using Verilog HDL

Verilog HDL vs VHDL

Language Introduction and Applications

Data types, Operators

All Description Styles

Theory explanation Behavioral Modelling - Lab sessions

Dataflow Modelling - Lab sessions

Gate Level Modelling - Lab sessions

Switch Level Modelling - Lab sessions

Types of Procedural Statements

Types of Continuous Statements

Blocking and Non-Blocking Assignments - Lab Sessions

Introducing the Process of Synthesis Coding

RTL for Synthesis Modelling of Combinational Circuits

Adders, Subtractors, Ripple carry adder

Mux, Demux, Hierarchy models, Encoders, decoders

Latches, Flipflop, Registers

Counters RTL Design

FSMs & Memories

RTL Design and Verification of FIFO | RAM | RO

Testbench concepts for Verification from Basics to PRO

Verilog 1 week Challenge, Logical problem solving

Extra projects & Computer Architecture

Regular Assignments

Mock Tests

Interview Preparation

Module 3 - SystemVerilog for Verification

SystemVerilog Overview

Standard Data types & Literals & Operators

User-Defined Data types & Structures

Testbench Architecture & Connectivity

Testbench Components Static, Dynamic

Associative Arrays

Queues Tasks & Functions

Interfaces, Virtual Interface

Verification Features

Clocking Blocks, Mod ports

Object Oriented Programming

Classes | Objects

Polymorphism and Inheritance

Encapsulation, Abstract class, Dynamic class

Virtual class, Task, Function, Override methods

Randomization & Constraints

Constraint based verification practical examples

rand & randc, methods, enable, disable

SystemVerilog Coverage analysis

Code Coverage

Cross Coverage

Deep into Functional coverage

Toggle Coverage

Assertion Based Verification (ABV)

Immediate assertion

Concurrent assertion

Module 4 - UVM for Verification

In depth of UVM in SOC | IP level Verification

Detailed explanation on UVC in SOC | IP Verification

Introduction to UVM, Features

Testbench Hierarchy, Components

UVM Sequence Item, Sequence, Sequencer

Configuration, UVM config_db

Factory registration, Factory override

UVM Phases, UVM Driver

UVM Monitor

UVM Agent

DTPs (Detailed Test Plan Explanation)

Testcase scenarios

Detailed feature wise test implementation

Deep into TLM Ports, Configuration database

UVM Concepts Lab sessions

More into developing RTL Design & Creating UVM Tb environment for Adders, Memories, Registers

Developing Test plan, Test cases, Test suits

Deep into Coverage & Assertions in UVM testbench

Debugging techniques

Our own testcase development for Protocol designs

Creating RAL models for Memories

All topics theory + Lab sessions

Regular assignments

Mock tests

Interview Preparation

Module 5-Projects & Protocols

Protocols & Projects

Protocol 1 - UART Protocol - RTL Design Using Verilog HDL

Theory

Introduction to UART Protocol: Features and Applications
Functional Block Diagram of UART
Signal Definitions and Timing Diagram

Implementation

Transmitter Design: FSM Implementation, Baud Rate Generator
Receiver Design: FSM Implementation, Data Sampling
RTL Coding of UART Transmitter and Receiver
Testbench Creation
Simulation, Debugging, and Waveform Analysis

Protocol 2 - I2C Protocol Implementation and Verification

Theory

I2C Protocol Overview: Features, Signals, and Modes of Operation
Multi-Master and Multi-Slave Configurations
Timing Diagram and Bit-Level Analysis

Implementation

RTL Design of I2C Controller
Writing Test Cases in SystemVerilog
Testbench Creation and Verification using SystemVerilog
Coverage Metrics and Analysis

Protocols - AMBA Protocols (APB, AHB, AXI)

Theory

Deep Dive into AMBA Protocols: Overview and Features
Detailed Signal Features of APB, AHB, and AXI Protocols
Comparison and Use Cases in Industry
Functional Features of APB, AHB, and AXI
Detailed Understanding of Master & Slave Transactions
Pipeline & Non-Pipeline Structure, Burst Transfers
Out-of-Order Transaction Features, Multiple Outstanding Transactions

Implementation

APB Protocol: RTL Design and Verification using SystemVerilog
AHB Protocol: RTL Design and UVM-Based Verification
AXI Protocol: Advanced RTL Design and UVM-Based Verification
Developing Comprehensive Test Plans and Writing Test Cases
Debugging and Coverage Analysis for AMBA Protocols
Developing Custom Testcases and Testplans

3 Major Projects - Selective Projects

DMA Controller
RISC-V Processor with Pipeline Stages
1×3 Router in UVM
DDR Memory
4-Port Calculator

Module 6 - Perl Scripting

Introduction to Linux Setup

Importance of Perl Scripting

How to Run the Commands

Automating Simulation Runs

Perl + EDA Tools

Idea on Coverage Analysis

UVM / Verification Environment Automation

Configurable UVM Testbench Generator

Upload and Extract the Coverage Report

Walk Through Perl Concepts

Coding Standards

Importance of Regressions | How to Run the Regression

How to Check Test Pass or Fail in SOC | IP Level

Idea on Debugging Testcases, Execution Flow

Module 7 - SOC level Verification & debugging techniques

Design a Processor-based SOC, which involves Memory Controller, DDR Memory, and IO Peripherals

AXI Bus Connection in a SOC Design

RTL Design of Each Block and Verification of Every Block using SystemVerilog & UVM Methodology

Deep into Industrial Approaches

Development of Linux Environment and Running Regressions

Coverage & Assertion-Based Verification

SOC | IP Level Verification Techniques, Writing C-Based Testcases

Module 8 - Aptitude & Logical reasoning + Communication Skills

Aptitude

Logical Reasoning

Problem Solving

Puzzle Solving

Communication Skills, Interview Practice

DLD, Verilog, SV, UVM, Projects, Protocols Mock Interviews

Way of Explanation Practice

Interview Ready

System on Chip Design

Introduction to System on Chip Design

SOC Verification vs IP Verification

Verification approaches at Industry level

Pre silicon vs Post silicon Verification

Verification vs Validation

ASIC Design & Verification

What Skills Will You Be Learning in the Next Six Months?

Module 0

Module 1 3 Weeks

Module 2 1.5 Month

Module 3 1.5 Month

Module 4 1.5 Month

Module 5 1.5 Month

Module 6 2 Weeks

Module 7 1 Week

Module 8 1 Month

Tools Access

Module 0 : Introduction to VLSI Design

Course Modules

Module 1 - Advanced Digital Logic Design

Module 2 - RTL Design using Verilog HDL

Module 3 - SystemVerilog for Verification

Module 4 - UVM for Verification

Module 5-Projects & Protocols

Protocols & Projects

Protocol 1 - UART Protocol - RTL Design Using Verilog HDL

Theory

Implementation

Protocol 2 - I2C Protocol Implementation and Verification

Theory

Implementation

Protocols - AMBA Protocols (APB, AHB, AXI)

Theory

Implementation

3 Major Projects - Selective Projects

Module 6 - Perl Scripting

Module 7 - SOC level Verification & debugging techniques

Module 8 - Aptitude & Logical reasoning + Communication Skills

System on Chip Design

Courses

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