Advanced ASIC Design & Verification

Job oriented Training + Industrial Guidance + Placement Assistance

Gain hands-on expertise in ASIC DESIGN & VERIFICATION, mastering industry tools and methodologies for a successful career

Demo Sessions - Introduction to VLSI Design

Overview of VLSI Design Flow

Complete understanding of the VLSI design process from concept to silicon

Frontend Domain vs Backend Domain

Clear distinction between frontend and backend roles in VLSI design

Discussion on Industry Requirements

Insights into current industry demands and skill expectations

FPGA vs ASIC vs SOC Designs

Comparative analysis of different design approaches and their applications

Moore's Law and Nanometer Technology

Understanding semiconductor scaling and its implications

Importance of Digital Electronics

Foundation concepts essential for VLSI design and verification

Introduction to RTL Design & Verification

Getting started with Register Transfer Level design and verification methodologies

Course Module

Module 1 -Advanced Digital Logic Design

Glitches & Hazards

Interview Preparation

Regular Assignments

Mock tests

Interview Preparation

Module 2 - RTL Design using Verilog HDL

Language Basics and Applications

Data Types, Operators, and Syntax

All Description Styles – Theory explanation

Behavioral Modeling

Dataflow Modelling - Lab sessions

Gate Level Modelling - Lab sessions

Switch Level Modelling - Lab sessions

Types of Procedural Statements

Types of Continuous Statements

Blocking and Non-Blocking Assignments - Lab Sessions

Introducing the Process of Synthesis

Coding RTL for Synthesis

Modelling of Combinational Circuits, Latches, Flipflop, Registers, Counters

Registers, Counters

Regular Assignments, Mock Tests

Interview Preparation

Module 3 - SystemVerilog for Verification

SystemVerilog Overview

Standard Data types & Literals & Operators

User-Defined Data types & Structures

Testbench Architecture & Connectivity

Testbench Components

Static, Dynamic, Associative Arrays

Queues

Tasks & Functions

Interfaces, Virtual Interface Verification Features

Clocking Blocks, Mod ports

Object Oriented Programming, Classes | Objects

Polymorphism and Virtuality

Inheritance, Encapsulation

Random Stimulus

Class-Based Random Stimulus

Systemverilog Coverage analysis

Code Coverage, Cross Coverage

Deep into Functional coverage

Toggle Coverage

Assertion Based Verification(ABV)

SystemVerilog Assertions

Direct Programming Interface(DPI)

Interprocess Synchronization

Testbench Components

Testbench Examples

Testplans, Testcases

All topics theory + Lab sessions

Regular assignments

Mock tests

Interview Preparation

Module 4 - UVM for Verification

Indepth of UVM in SOC | IP level Verification

Detailed explanation on UVC in SOC | IP Verification

Introduction to UVM, Features

Testbench Hierarchy, Components

UVM Sequence Item, Sequence, Sequencer

Configuration, UVM config_db

UVM Phases

UVM Driver

UVM Monitor

UVM Agent

DTPs (Detailed Test Plan Explanation)

Testcase scenarios

Detailed feature wise test implementation

All topics theory + Lab sessions

Regular assignments

Mock tests

Interview Preparation

Module 5 - Scripting Language - Perl

Introduction to Linux Setup

Importance of Perl Scripting

How to run the commands

Idea on Coverage analysis

Upload and extract the coverage report

Walk through perl concepts

Coding standards

Importance of Regressions | How to Run the Regression

How to check test pass or fail in SOC | IP Level

Idea on debugging testcases, execution flow

Module 6 - Advanced SV & UVM Lab Sessions

Deep into Object oriented programing Problem Statements

Advanced Coverage Analysis

Industry insights of Coverage driven verification

Assertion based verification Problem statements

SV Testbench creation for Various designs

Deep into Coverage & Assertions based verification

Development of Test plan, Test cases and Test suits

Verification Environment for a Protocol Design

Running regression suits & Debugging techniques

Deep into TLM Ports, Configuration database and all UVM

Concepts Lab sessions

More into developing RTL Design & Creating UVM Tb environment for Adders, Memories, Registers

Developing Test plan, Test cases, Test suits

Deep into Coverage & Assertions in UVM testbench

Debugging techniques

Our own testcase development for Protocol designs & Creating RAL models for Memories

Module 7 - SOC Design & Verification

Going to Design a Processor based SOC., which involves Memory controller, DDR Memory and IO Peripherals

AXI Bus connection in a SOC Design

RTL Design of each block and verification of every block using Systemverilog & UVM Methodology

Deep into Industrial approaches, Development of Linux Environment and running regressions

Coverage & Assertion based Verification

SOC | IP level Verification techniques, writing C based testcases

Module 8 - Projects & Protocols

Project 1 - UART Protocol - RTL Design Using Verilog HDL

Theory

Introduction to UART Protocol: Features and Applications
Functional Block Diagram of UART
Signal Definitions and Timing Diagram

Implementation

Transmitter Design: FSM Implementation, Baud Rate Generator
Receiver Design: FSM Implementation, Data Sampling
RTL Coding of UART Transmitter and Receiver using Verilog HDL
Testbench Creation and Simulation
Debugging and Waveform Analysis

Project 2 - I2C Protocol Implementation and Verification

Theory

I2C Protocol Overview: Features, Signals, and Modes of Operation
Multi-Master and Multi-Slave Configurations
Timing Diagram and Bit-Level Analysis

Implementation

RTL Design of I2C Controller
Writing Test Cases in SystemVerilog
Testbench Creation and Verification using SystemVerilog
Coverage Metrics and Analysis

Project 3 - AMBA Protocols (APB, AHB, AXI)

Theory

Deep Dive into AMBA Protocols: Overview and Features
Detailed Signal Features of APB, AHB, and AXI Protocols
Comparison and Use Cases in Industry

Implementation

APB Protocol: RTL Design and Verification using SystemVerilog
AHB Protocol: RTL Design and UVM-Based Verification
AXI Protocol: Advanced RTL Design and UVM-Based Verification
Developing Comprehensive Test Plans and Writing Test Cases
Debugging and Coverage Analysis for AMBA Protocols

Project 4 - 3 Major Projects

Selective Projects

DMA Controller
Router
Digital Alarm, Traffic light controller
4 Port Calculator
RISC V Project

Implementation

All Projects are implemented in RTL design & Verification using SV, UVM

Module 9 - Advanced Client Level Projects

Project 1 - DDR2 to DDR5 Theory & Hands-on Sessions

Theory

Introduction to DDR Memories
What is DDR? (Double Data Rate)
Differences between DDR2, DDR3, DDR4, DDR5
Applications in real-world systems
Architecture Overview
Memory controller design
Timing parameters (CAS latency, refresh cycles)
Data transfer mechanisms (Burst operations, prefetch)

Beginner-Friendly Project

Basic DDR read/write operation explanation
State machine for DDR controller (simplified version)
Example project: DDR3 read/write model

Comparison

Evolution from DDR2 → DDR5
Power efficiency, bandwidth improvements

RTL Design of DDR Controller

Command decoder
Bank management
Address mapping
Data path design

SystemVerilog Verification

Writing a DDR memory model
Testbench architecture
Assertions for timing checks
Coverage for read/write/refresh operations

Project

RTL design of simplified DDR controller
Verification using constrained random tests

Industry Insights

DDR in SoC design
Verification challenges in high-speed memory

Project 2 - PCIe Gen 3 to Gen 6

Theory

PCIe Overview, Evolution & Protocol Stack
Deep into Transaction Layer Protocol
Data Link Layer & Basic Reliability
Physical Layer and LTSSM (Link Training and Status State Machine)
PCIe Gen6 Advanced Signaling

Advanced Concepts

Gen3 Improvements
Gen4 Enhancements
Advanced Flow Control & Virtualization
Gen5 Changes
PCIe Gen6 Overview - FLIT Mode
PCIe Gen6 Error Recovery - Low Latency Retry
Security and Integrity
CXL on PCIe 5.0/6.0
Hands-on Sessions, Tracks
Testflow Execution, Error Debugging
Interview Preparation

Why ProV Logic ?

Structured
Course
Curriculum

Tool Access
Lab Sessions

Mock Interviews
Resume guide

Best Live Sessions
Doubt discussions

1:1 Mentorship

Placement
Guaranteed

Advanced ASIC Design & Verification

Demo Sessions - Introduction to VLSI Design

Overview of VLSI Design Flow

Frontend Domain vs Backend Domain

Discussion on Industry Requirements

FPGA vs ASIC vs SOC Designs

Moore's Law and Nanometer Technology

Importance of Digital Electronics

Introduction to RTL Design & Verification

Course Module

Module 1 -Advanced Digital Logic Design

Module 2 - RTL Design using Verilog HDL

Module 3 - SystemVerilog for Verification

Module 4 - UVM for Verification

Module 5 - Scripting Language - Perl

Module 6 - Advanced SV & UVM Lab Sessions

Module 7 - SOC Design & Verification

Module 8 - Projects & Protocols

Project 1 - UART Protocol - RTL Design Using Verilog HDL

Theory

Implementation

Project 2 - I2C Protocol Implementation and Verification

Theory

Implementation

Project 3 - AMBA Protocols (APB, AHB, AXI)

Theory

Implementation

Project 4 - 3 Major Projects

Selective Projects

Implementation

Module 9 - Advanced Client Level Projects

Project 1 - DDR2 to DDR5 Theory & Hands-on Sessions

Theory

Beginner-Friendly Project

Comparison

RTL Design of DDR Controller

SystemVerilog Verification

Project

Industry Insights

Project 2 - PCIe Gen 3 to Gen 6

Theory

Advanced Concepts

Why ProV Logic ?

Courses

Company

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