VLSI PHYSICAL DESIGN

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What Skills Will You Be Learning in the Next Six Months?

Module 0

Introduction to VLSI

Module 1 3 Weeks

Advanced Digital Logic Design

Module 2 1.5 Month

RTL Design using Verilog HDL

Module 3 3 Months

Physical Design Flow

Module 4 2 Weeks

Linux, TCL/Tk Scripting

Module 5 2 Weeks

RTL to GDSII Flow
DFT Insertion & Basic Concepts Discussion

Module 6 1 Month

Minor & Major Projects and Protocols

Module 7 1 Week

SOC Level Design Understanding

Module 8 1 Month

Aptitude & Logical Reasoning
Communication Skills Building, Mock Interviews
Revision of Digital Electronics, Verilog HDL, Physical Design Flow, TCL
Projects – 1:1 Mock

Tools Access

Siemens, Synopsys, Xilinx, Cadence

Module 0 : Introduction to VLSI Design

Overview of VLSI Design Flow
Frontend Domain vs Backend Domain
Discussion on Industry Requirements
Moore Law, Nano meter Technology
FPGA vs ASIC vs SoC Designs
SoC vs Subsystem vs IP Level Verification
Future of VLSI – What Next Big Thing in VLSI?
Importance of Digital Electronics
Introduction to RTL Design & Verification

Course Modules

Module 1 - Advanced Digital Logic Design

All concepts from scratch

Number systems, Conversions

Logic gates, Universal gates

Boolean Algebra, K-maps

All type of Combinational logic circuits

All type of Sequential logic circuits

Shift Registers

Counters designs

FSMs and Its Application examples

Memories

Static Timing Analysis

CMOS Logic Design

Glitches & Hazards

Interview Preparation Regular Assignments

Mock tests Interview Preparation

Module 2 - RTL Design using Verilog HDL

Verilog HDL vs VHDL

Language Introduction and Applications

Data types, Operators

All Description Styles

Theory explanation Behavioral Modelling - Lab sessions

Dataflow Modelling - Lab sessions

Gate Level Modelling - Lab sessions

Switch Level Modelling - Lab sessions

Types of Procedural Statements

Types of Continuous Statements

Blocking and Non-Blocking Assignments - Lab Sessions

Introducing the Process of Synthesis Coding

RTL for Synthesis Modelling of Combinational Circuits

Adders, Subtractors, Ripple carry adder

Mux, Demux, Hierarchy models, Encoders, decoders

Latches, Flipflop, Registers

Counters RTL Design

FSMs & Memories

RTL Design and Verification of FIFO | RAM | RO

Testbench concepts for Verification from Basics to PRO

Verilog 1 week Challenge, Logical problem solving

Extra projects & Computer Architecture

Regular Assignments

Mock Tests

Interview Preparation

Module 3 - Physical Design Flow

Advanced Physical Design - Complete Topics

Overview of Advanced Physical Design

Floor Planning and Power Planning

• Advanced Floorplanning Strategies

• Macro Placement Optimization

• Pin and IO Placement

• Hierarchical vs. Flat Floorplanning

• Advanced Power Grid Design

• Dynamic Power Analysis

• Low-Power Techniques (Dynamic Voltage Scaling, Multi-Vt)

• Case Study: Power Planning for High-Performance Chips

Placement

• Timing-Driven Placement

• Congestion Estimation and Mitigation

• Machine Learning Techniques in Placement Optimization

• Multi-Die Placement in 3D ICs

• Density Optimization and Design Closure

• Lab: Placement Optimization Using Industry Tools

Clock Tree Synthesis (CTS)

• Advanced Clock Tree Design

• Low-Skew and Low-Latency Clock Trees

• Mesh vs. H-Tree vs. Clock Gating

• Clock Domain Crossing (CDC) Challenges

• Multi-Corner Multi-Mode (MCMM) CTS Techniques

• Power-Aware CTS

• Lab: Advanced CTS Implementation in EDA Tools

Routing

• Advanced Routing Algorithms

• Crosstalk and Noise-Aware Routing

• Multi-Layer and 3D Routing

• Power and Clock Routing Optimization

• Lab: Detailed Routing and Optimization in Advanced Nodes

Timing and Signal Integrity

• Advanced Static Timing Analysis (STA)

• Multi-Mode Multi-Corner Analysis

• Path-Based Analysis (PBA)

• Clock Skew, Jitter, and Timing Closure

• Signal Integrity Challenges and Mitigation

• Lab: Timing Optimization and SI Analysis

Power and Thermal Analysis

• Advanced IR Drop Analysis

• Power Grid Optimization at Advanced Nodes

• Thermal Analysis and Hotspot Mitigation

• Electrostatic Discharge (ESD) Protection

• Lab: Power and Thermal Analysis with Signoff Tools

Physical Verification

• Advanced LVS and DRC Techniques

• Parasitic Extraction and Post-Layout Simulation

• Physical Verification for FinFET and 3D ICs

• Signoff Tools and Methodologies

• Lab: Physical Verification of an Advanced Node Design

VLSI Backend Design Flow

Advanced Technology Nodes (7nm, 5nm, 3nm, etc.)

Challenges in Modern Physical Design

Foundry and Process Design Kits (PDK)

Case Study: Advanced Nodes in Real-World Designs

Module 4 - TCL Scripting

Introduction to TCL

Substitution and Data Types

Fundamentals of TCL Scripting

Variables, Loops, and Conditionals Procedures and Functions

TCL in EDA Tools

Operators and Decision Making

Loops and Arrays

String and List Handling

Procedures and Functions

File Handling and Regular Expressions

Application-oriented TCL Scripting - Floorplan, Placement, Routing, Clock Tree Synthesis (CTS)

Introduction to Linux Essentials

Linux Commands and Text Editors

Shell Scripting Environment Setup

Version Control with Git

Module 5-RTL to GDSII Flow Projects

Protocols & Projects

Protocol 1 - UART Protocol - RTL Design Using Verilog HDL

Theory

Introduction to UART Protocol: Features and Applications
Functional Block Diagram of UART
Signal Definitions and Timing Diagram

Implementation

PD Flow design - RTL to GDS

Protocol 2 - I2C Protocol Implementation and Verification

Theory

I2C Protocol Overview: Features, Signals, and Modes of Operation
Multi-Master and Multi-Slave Configurations
Timing Diagram and Bit-Level Analysis

Implementation

PD Flow design - RTL to GDS

Protocol 3 - AMBA APB AHB AXI

Theory

Deep into specification explanation
Features of bus protocols
Pipeline & Non-pipeline structure
Detailed understanding on Master & Slave transactions

Module 6 - Projects & Protocols

3 Major Projects - Selective Projects

Capstone Project

Physical Design & Implementation on RISC-V Core Design

Physical Verification of RISC-V Design

Router 1×3 Block Level Physical Design

Pipeline Design (Adder / Multiplier)

Module 7 - SOC level Verification & debugging techniques

Design a Processor based SoC (Memory controller, DDR memory & I/O peripherals)

AXI bus connection in a SoC design

RTL design of each block and verification of every block

Verification using SystemVerilog & UVM methodology

Deep dive into industrial approaches and best practices

Development of Linux environment and running regressions

Module 8 - Aptitude & Logical reasoning + Communication Skills

Aptitude

Logical Reasoning

Problem Solving

Puzzle Solving

Communication Skills & Interview Practice

DLD, Verilog, SystemVerilog, UVM, Projects, Protocols Mock Interviews

Way of Explanation Practice | Interview Ready

System on Chip Design

Introduction to System on Chip Design

SOC Verification vs IP Verification

Verification approaches at Industry level

Pre silicon vs Post silicon Verification

Verification vs Validation

VLSI PHYSICAL DESIGN

What Skills Will You Be Learning in the Next Six Months?

Module 0

Module 1 3 Weeks

Module 2 1.5 Month

Module 3 3 Months

Module 4 2 Weeks

Module 5 2 Weeks

Module 6 1 Month

Module 7 1 Week

Module 8 1 Month

Tools Access

Module 0 : Introduction to VLSI Design

Course Modules

Module 1 - Advanced Digital Logic Design

Module 2 - RTL Design using Verilog HDL

Module 3 - Physical Design Flow

Advanced Physical Design - Complete Topics

Module 4 - TCL Scripting

Module 5-RTL to GDSII Flow Projects

Protocols & Projects

Protocol 1 - UART Protocol - RTL Design Using Verilog HDL

Theory

Implementation

Protocol 2 - I2C Protocol Implementation and Verification

Theory

Implementation

Protocol 3 - AMBA APB AHB AXI

Theory

Module 6 - Projects & Protocols

Module 7 - SOC level Verification & debugging techniques

Module 8 - Aptitude & Logical reasoning + Communication Skills

System on Chip Design

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